forked from Openwrt/openwrt
af1fc05cad
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. See: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html for the original discussion. Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
289 lines
6.5 KiB
Diff
289 lines
6.5 KiB
Diff
From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001
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From: Calvin Johnson <calvin.johnson@nxp.com>
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Date: Sat, 16 Sep 2017 14:20:23 +0530
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Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support
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Update ls1012a dtsi and platform dts files with support for ppfe.
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Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
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Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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---
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.../boot/dts/freescale/fsl-ls1012a-frdm.dts | 43 +++++++++++++++++
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.../boot/dts/freescale/fsl-ls1012a-frwy.dts | 43 +++++++++++++++++
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.../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 +++++++++++++++++
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.../boot/dts/freescale/fsl-ls1012a-rdb.dts | 47 +++++++++++++++++++
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.../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++
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5 files changed, 205 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
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@@ -14,6 +14,11 @@
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model = "LS1012A Freedom Board";
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compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
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+ aliases {
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+ ethernet0 = &pfe_mac0;
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+ ethernet1 = &pfe_mac1;
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+ };
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+
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sys_mclk: clock-mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -95,6 +100,44 @@
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};
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};
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+&pfe {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ pfe_mac0: ethernet@0 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x1>; /* enabled/disabled */
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+ };
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+ };
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+
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+ pfe_mac1: ethernet@1 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x0>; /* enabled/disabled */
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+ };
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+ };
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+};
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+
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&qspi {
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status = "okay";
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
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@@ -14,6 +14,11 @@
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/ {
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model = "LS1012A FRWY Board";
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compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
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+
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+ aliases {
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+ ethernet0 = &pfe_mac0;
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+ ethernet1 = &pfe_mac1;
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+ };
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};
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&duart0 {
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@@ -28,6 +33,44 @@
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status = "okay";
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};
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+&pfe {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ pfe_mac0: ethernet@0 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x1>; /* enabled/disabled */
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+ };
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+ };
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+
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+ pfe_mac1: ethernet@1 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x0>; /* enabled/disabled */
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+ };
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+ };
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+};
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+
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&qspi {
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status = "okay";
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
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@@ -18,6 +18,11 @@
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mmc1 = &esdhc1;
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};
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+ aliases {
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+ ethernet0 = &pfe_mac0;
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+ ethernet1 = &pfe_mac1;
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+ };
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+
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sys_mclk: clock-mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -132,6 +137,44 @@
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};
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};
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};
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+
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+&pfe {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ pfe_mac0: ethernet@0 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x2>;
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+ phy-mode = "sgmii-2500";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x1>; /* enabled/disabled */
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+ };
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+ };
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+
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+ pfe_mac1: ethernet@1 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x3>;
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+ phy-mode = "sgmii-2500";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x0>; /* enabled/disabled */
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+ };
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+ };
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+};
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&qspi {
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status = "okay";
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
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@@ -16,6 +16,8 @@
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aliases {
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serial0 = &duart0;
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+ ethernet0 = &pfe_mac0;
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+ ethernet1 = &pfe_mac1;
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mmc0 = &esdhc0;
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mmc1 = &esdhc1;
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};
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@@ -86,6 +88,44 @@
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};
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};
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+&pfe {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ pfe_mac0: ethernet@0 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x1>; /* enabled/disabled */
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+ };
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+ };
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+
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+ pfe_mac1: ethernet@1 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>; /* GEM_ID */
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+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
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+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "rgmii-txid";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x0>; /* enabled/disabled */
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+ };
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+ };
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+};
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+
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&qspi {
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status = "okay";
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
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@@ -568,6 +568,35 @@
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};
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};
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ pfe_reserved: packetbuffer@83400000 {
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+ reg = <0 0x83400000 0 0xc00000>;
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+ };
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+ };
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+
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+ pfe: pfe@04000000 {
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+ compatible = "fsl,pfe";
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+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
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+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
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+ reg-names = "pfe", "pfe-ddr";
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+ fsl,pfe-num-interfaces = <0x2>;
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+ interrupts = <0 172 0x4>, /* HIF interrupt */
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+ <0 173 0x4>, /*HIF_NOCPY interrupt */
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+ <0 174 0x4>; /* WoL interrupt */
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+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
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+ memory-region = <&pfe_reserved>;
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+ fsl,pfe-scfg = <&scfg 0>;
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+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
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+ clocks = <&clockgen 4 0>;
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+ clock-names = "pfe";
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+
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+ status = "okay";
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+ };
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+
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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