forked from Openwrt/openwrt
13cdc8955c
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.80 Manually rebased: generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch[1] All other patches automatically rebased. 1. Acknowledgement to @heheb and @DragonBluep. Upstream commit for ref: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.80&id=9c5662e95a8dcc232c3ef4deb21033badcd260f6 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me>
44 lines
1.5 KiB
Diff
44 lines
1.5 KiB
Diff
From 2b1b8c4c215af7988136401c902338d091d408a1 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Mon, 3 Apr 2023 01:21:57 +0300
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Subject: [PATCH 2/2] net: phy: realtek: disable SGMII in-band AN for 2.5G PHYs
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MAC drivers don't use SGMII in-band autonegotiation unless told to do so
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in device tree using 'managed = "in-band-status"'. When using MDIO to
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access a PHY, in-band-status is unneeded as we have link-status via
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MDIO. Switch off SGMII in-band autonegotiation using magic values.
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Reported-by: Chen Minqiang <ptpt52@gmail.com>
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Reported-by: Chukun Pan <amadeus@jmu.edu.cn>
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Reported-by: Yevhen Kolomeiko <jarvis2709@gmail.com>
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Tested-by: Yevhen Kolomeiko <jarvis2709@gmail.com>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/phy/realtek.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -885,6 +885,7 @@ static irqreturn_t rtl9000a_handle_inter
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static int rtl8221b_config_init(struct phy_device *phydev)
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{
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u16 option_mode;
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+ int val;
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_2500BASEX:
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@@ -921,6 +922,13 @@ static int rtl8221b_config_init(struct p
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break;
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}
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+ /* Disable SGMII AN */
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7588, 0x2);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7589, 0x71d0);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7587, 0x3);
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+ phy_read_mmd_poll_timeout(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7587,
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+ val, !(val & BIT(0)), 500, 100000, false);
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+
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return 0;
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}
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