forked from Openwrt/openwrt
fe9d2ccbc3
Move accepted patches to backport folder, re-add previously removed patch
which caused havoc on MT7621 and add the (still pending) fix.
Fixes: d40691a5fb ("generic: 6.1, 6.6: mt7530: import pending patches")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
201 lines
7.7 KiB
Diff
201 lines
7.7 KiB
Diff
From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Mon, 22 Apr 2024 10:15:09 +0300
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Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
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MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
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for MT7530 only. Add MT7530 prefix to the definition for bit 15.
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Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
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Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
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follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
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"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
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Generation Router Platform: Datasheet (Open Version) v0.1" documents.
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These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
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with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
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Remove PMCR_SPEED_MASK which doesn't have a use.
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Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
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end for the mask that includes all force mode definitions.
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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---
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drivers/net/dsa/mt7530.c | 24 ++++++++---------
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drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
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2 files changed, 42 insertions(+), 40 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -896,7 +896,7 @@ static void mt7530_setup_port5(struct ds
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val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
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/* Setup the MAC by default for the cpu port */
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- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
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+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
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break;
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case P5_INTF_SEL_GMAC5:
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/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
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@@ -2444,8 +2444,8 @@ mt7530_setup(struct dsa_switch *ds)
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/* Clear link settings and enable force mode to force link down
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* on all ports until they're enabled later.
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*/
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- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
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- PMCR_FORCE_MODE, PMCR_FORCE_MODE);
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+ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
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+ MT7530_FORCE_MODE, MT7530_FORCE_MODE);
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/* Disable forwarding by default on all ports */
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mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
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@@ -2555,8 +2555,8 @@ mt7531_setup_common(struct dsa_switch *d
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/* Clear link settings and enable force mode to force link down
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* on all ports until they're enabled later.
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*/
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- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
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- MT7531_FORCE_MODE, MT7531_FORCE_MODE);
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+ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
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+ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
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/* Disable forwarding by default on all ports */
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mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
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@@ -2639,7 +2639,7 @@ mt7531_setup(struct dsa_switch *ds)
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/* Force link down on all ports before internal reset */
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for (i = 0; i < MT7530_NUM_PORTS; i++)
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- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
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+ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
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/* Reset the switch through internal reset */
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mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
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@@ -2881,7 +2881,7 @@ mt753x_phylink_mac_config(struct phylink
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/* Are we connected to external phy */
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if (port == 5 && dsa_is_user_port(ds, 5))
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- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
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+ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
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}
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static void mt753x_phylink_mac_link_down(struct phylink_config *config,
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@@ -2891,7 +2891,7 @@ static void mt753x_phylink_mac_link_down
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struct dsa_port *dp = dsa_phylink_to_port(config);
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struct mt7530_priv *priv = dp->ds->priv;
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- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
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+ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
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}
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static void mt753x_phylink_mac_link_up(struct phylink_config *config,
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@@ -2905,7 +2905,7 @@ static void mt753x_phylink_mac_link_up(s
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struct mt7530_priv *priv = dp->ds->priv;
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u32 mcr;
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- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
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+ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
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switch (speed) {
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case SPEED_1000:
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@@ -2920,9 +2920,9 @@ static void mt753x_phylink_mac_link_up(s
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if (duplex == DUPLEX_FULL) {
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mcr |= PMCR_FORCE_FDX;
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if (tx_pause)
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- mcr |= PMCR_TX_FC_EN;
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+ mcr |= PMCR_FORCE_TX_FC_EN;
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if (rx_pause)
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- mcr |= PMCR_RX_FC_EN;
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+ mcr |= PMCR_FORCE_RX_FC_EN;
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}
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if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
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@@ -2937,7 +2937,7 @@ static void mt753x_phylink_mac_link_up(s
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}
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}
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- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
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+ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
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}
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static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
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#define G0_PORT_VID_DEF G0_PORT_VID(0)
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/* Register for port MAC control register */
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-#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
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-#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
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+#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
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+#define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
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+#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
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#define PMCR_EXT_PHY BIT(17)
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#define PMCR_MAC_MODE BIT(16)
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-#define PMCR_FORCE_MODE BIT(15)
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-#define PMCR_TX_EN BIT(14)
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-#define PMCR_RX_EN BIT(13)
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+#define MT7530_FORCE_MODE BIT(15)
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+#define PMCR_MAC_TX_EN BIT(14)
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+#define PMCR_MAC_RX_EN BIT(13)
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#define PMCR_BACKOFF_EN BIT(9)
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#define PMCR_BACKPR_EN BIT(8)
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#define PMCR_FORCE_EEE1G BIT(7)
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#define PMCR_FORCE_EEE100 BIT(6)
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-#define PMCR_TX_FC_EN BIT(5)
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-#define PMCR_RX_FC_EN BIT(4)
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+#define PMCR_FORCE_RX_FC_EN BIT(5)
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+#define PMCR_FORCE_TX_FC_EN BIT(4)
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#define PMCR_FORCE_SPEED_1000 BIT(3)
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#define PMCR_FORCE_SPEED_100 BIT(2)
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#define PMCR_FORCE_FDX BIT(1)
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#define PMCR_FORCE_LNK BIT(0)
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-#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
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- PMCR_FORCE_SPEED_1000)
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-#define MT7531_FORCE_LNK BIT(31)
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-#define MT7531_FORCE_SPD BIT(30)
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-#define MT7531_FORCE_DPX BIT(29)
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-#define MT7531_FORCE_RX_FC BIT(28)
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-#define MT7531_FORCE_TX_FC BIT(27)
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-#define MT7531_FORCE_EEE100 BIT(26)
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-#define MT7531_FORCE_EEE1G BIT(25)
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-#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
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- MT7531_FORCE_SPD | \
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- MT7531_FORCE_DPX | \
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- MT7531_FORCE_RX_FC | \
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- MT7531_FORCE_TX_FC | \
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- MT7531_FORCE_EEE100 | \
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- MT7531_FORCE_EEE1G)
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-#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
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- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
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- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
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- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
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- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
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+#define MT7531_FORCE_MODE_LNK BIT(31)
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+#define MT7531_FORCE_MODE_SPD BIT(30)
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+#define MT7531_FORCE_MODE_DPX BIT(29)
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+#define MT7531_FORCE_MODE_RX_FC BIT(28)
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+#define MT7531_FORCE_MODE_TX_FC BIT(27)
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+#define MT7531_FORCE_MODE_EEE100 BIT(26)
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+#define MT7531_FORCE_MODE_EEE1G BIT(25)
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+#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
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+ MT7531_FORCE_MODE_SPD | \
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+ MT7531_FORCE_MODE_DPX | \
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+ MT7531_FORCE_MODE_RX_FC | \
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+ MT7531_FORCE_MODE_TX_FC | \
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+ MT7531_FORCE_MODE_EEE100 | \
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+ MT7531_FORCE_MODE_EEE1G)
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+#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
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+ PMCR_FORCE_EEE1G | \
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+ PMCR_FORCE_EEE100 | \
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+ PMCR_FORCE_RX_FC_EN | \
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+ PMCR_FORCE_TX_FC_EN | \
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+ PMCR_FORCE_SPEED_1000 | \
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+ PMCR_FORCE_SPEED_100 | \
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+ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
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#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
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#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
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