forked from Openwrt/openwrt
f3d2829b51
Backport a bunch of fixes and improvements for WED and PPE, mostly for MT7988. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
92 lines
3.2 KiB
Diff
92 lines
3.2 KiB
Diff
From 5f5997322584b6257543d4d103f81484b8006d84 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Fri, 17 Nov 2023 17:42:59 +0100
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Subject: [PATCH 4/5] net: ethernet: mtk_wed: add support for devices with more
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than 4GB of dram
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Introduce WED offloading support for boards with more than 4GB of
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memory.
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Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
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Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/1c7efdf5d384ea7af3c0209723e40b2ee0f956bf.1700239272.git.lorenzo@kernel.org
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
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drivers/net/ethernet/mediatek/mtk_wed.c | 8 +++++---
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drivers/net/ethernet/mediatek/mtk_wed_wo.c | 3 ++-
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3 files changed, 11 insertions(+), 5 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -1158,15 +1158,18 @@ static int mtk_init_fq_dma(struct mtk_et
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phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
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for (i = 0; i < cnt; i++) {
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+ dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE;
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struct mtk_tx_dma_v2 *txd;
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txd = eth->scratch_ring + i * soc->tx.desc_size;
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- txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
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+ txd->txd1 = addr;
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if (i < cnt - 1)
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txd->txd2 = eth->phy_scratch_ring +
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(i + 1) * soc->tx.desc_size;
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txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
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+ if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
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+ txd->txd3 |= TX_DMA_PREP_ADDR64(addr);
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txd->txd4 = 0;
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if (mtk_is_netsys_v2_or_greater(eth)) {
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txd->txd5 = 0;
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--- a/drivers/net/ethernet/mediatek/mtk_wed.c
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+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
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@@ -691,10 +691,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
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for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
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struct mtk_wdma_desc *desc = desc_ptr;
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+ u32 ctrl;
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desc->buf0 = cpu_to_le32(buf_phys);
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if (!mtk_wed_is_v3_or_greater(dev->hw)) {
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- u32 txd_size, ctrl;
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+ u32 txd_size;
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txd_size = dev->wlan.init_buf(buf, buf_phys,
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token++);
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@@ -708,11 +709,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
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ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 |
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FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
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MTK_WED_BUF_SIZE - txd_size);
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- desc->ctrl = cpu_to_le32(ctrl);
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desc->info = 0;
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} else {
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- desc->ctrl = cpu_to_le32(token << 16);
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+ ctrl = token << 16 | TX_DMA_PREP_ADDR64(buf_phys);
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}
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+ desc->ctrl = cpu_to_le32(ctrl);
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desc_ptr += desc_size;
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buf += MTK_WED_BUF_SIZE;
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@@ -811,6 +812,7 @@ mtk_wed_hwrro_buffer_alloc(struct mtk_we
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buf_phys = page_phys;
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for (s = 0; s < MTK_WED_RX_BUF_PER_PAGE; s++) {
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desc->buf0 = cpu_to_le32(buf_phys);
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+ desc->token = cpu_to_le32(RX_DMA_PREP_ADDR64(buf_phys));
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buf_phys += MTK_WED_PAGE_BUF_SIZE;
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desc++;
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}
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--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.c
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+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.c
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@@ -142,7 +142,8 @@ mtk_wed_wo_queue_refill(struct mtk_wed_w
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dma_addr_t addr;
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void *buf;
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- buf = page_frag_alloc(&q->cache, q->buf_size, GFP_ATOMIC);
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+ buf = page_frag_alloc(&q->cache, q->buf_size,
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+ GFP_ATOMIC | GFP_DMA32);
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if (!buf)
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break;
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