forked from Openwrt/openwrt
156 lines
4.9 KiB
Diff
156 lines
4.9 KiB
Diff
From 2c1bdbc7e7560d7de754cad277d968d56bb1899e Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Tue, 23 Nov 2021 03:59:10 +0100
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Subject: net: dsa: qca8k: add support for mirror mode
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The switch supports mirror mode. Only one port can set as mirror port and
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every other port can set to both ingress and egress mode. The mirror
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port is disabled and reverted to normal operation once every port is
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removed from sending packet to it.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++
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drivers/net/dsa/qca8k.h | 4 +++
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2 files changed, 99 insertions(+)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -2046,6 +2046,99 @@ qca8k_port_mdb_del(struct dsa_switch *ds
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}
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static int
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+qca8k_port_mirror_add(struct dsa_switch *ds, int port,
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+ struct dsa_mall_mirror_tc_entry *mirror,
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+ bool ingress)
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+{
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+ struct qca8k_priv *priv = ds->priv;
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+ int monitor_port, ret;
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+ u32 reg, val;
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+
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+ /* Check for existent entry */
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+ if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
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+ return -EEXIST;
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+
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+ ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);
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+ if (ret)
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+ return ret;
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+
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+ /* QCA83xx can have only one port set to mirror mode.
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+ * Check that the correct port is requested and return error otherwise.
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+ * When no mirror port is set, the values is set to 0xF
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+ */
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+ monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
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+ if (monitor_port != 0xF && monitor_port != mirror->to_local_port)
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+ return -EEXIST;
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+
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+ /* Set the monitor port */
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+ val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,
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+ mirror->to_local_port);
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+ ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
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+ QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
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+ if (ret)
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+ return ret;
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+
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+ if (ingress) {
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+ reg = QCA8K_PORT_LOOKUP_CTRL(port);
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+ val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
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+ } else {
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+ reg = QCA8K_REG_PORT_HOL_CTRL1(port);
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+ val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
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+ }
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+
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+ ret = regmap_update_bits(priv->regmap, reg, val, val);
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+ if (ret)
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+ return ret;
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+
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+ /* Track mirror port for tx and rx to decide when the
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+ * mirror port has to be disabled.
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+ */
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+ if (ingress)
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+ priv->mirror_rx |= BIT(port);
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+ else
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+ priv->mirror_tx |= BIT(port);
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+
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+ return 0;
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+}
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+
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+static void
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+qca8k_port_mirror_del(struct dsa_switch *ds, int port,
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+ struct dsa_mall_mirror_tc_entry *mirror)
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+{
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+ struct qca8k_priv *priv = ds->priv;
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+ u32 reg, val;
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+ int ret;
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+
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+ if (mirror->ingress) {
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+ reg = QCA8K_PORT_LOOKUP_CTRL(port);
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+ val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
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+ } else {
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+ reg = QCA8K_REG_PORT_HOL_CTRL1(port);
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+ val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
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+ }
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+
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+ ret = regmap_clear_bits(priv->regmap, reg, val);
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+ if (ret)
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+ goto err;
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+
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+ if (mirror->ingress)
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+ priv->mirror_rx &= ~BIT(port);
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+ else
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+ priv->mirror_tx &= ~BIT(port);
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+
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+ /* No port set to send packet to mirror port. Disable mirror port */
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+ if (!priv->mirror_rx && !priv->mirror_tx) {
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+ val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);
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+ ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
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+ QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
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+ if (ret)
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+ goto err;
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+ }
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+err:
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+ dev_err(priv->dev, "Failed to del mirror port from %d", port);
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+}
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+
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+static int
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qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
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struct netlink_ext_ack *extack)
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{
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@@ -2155,6 +2248,8 @@ static const struct dsa_switch_ops qca8k
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.port_fdb_dump = qca8k_port_fdb_dump,
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.port_mdb_add = qca8k_port_mdb_add,
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.port_mdb_del = qca8k_port_mdb_del,
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+ .port_mirror_add = qca8k_port_mirror_add,
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+ .port_mirror_del = qca8k_port_mirror_del,
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.port_vlan_filtering = qca8k_port_vlan_filtering,
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.port_vlan_add = qca8k_port_vlan_add,
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.port_vlan_del = qca8k_port_vlan_del,
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -180,6 +180,7 @@
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#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
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#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
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#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
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+#define QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM GENMASK(7, 4)
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#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
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#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
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#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
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@@ -201,6 +202,7 @@
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#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
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#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
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#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
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+#define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
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#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
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#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
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@@ -305,6 +307,8 @@ struct qca8k_ports_config {
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struct qca8k_priv {
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u8 switch_id;
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u8 switch_revision;
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+ u8 mirror_rx;
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+ u8 mirror_tx;
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bool legacy_phy_port_mapping;
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struct qca8k_ports_config ports_config;
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struct regmap *regmap;
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