forked from Openwrt/openwrt
f631c7bbb1
Import commits from upstream Linux replacing some downstream patches.
Move accepted patches from pending-{5.15,6.1} to backport-{5.15,6.1}.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
133 lines
5.2 KiB
Diff
133 lines
5.2 KiB
Diff
From a1c9f7d1d24e90294f6a6755b137fcf306851e93 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 25 Jul 2023 01:53:28 +0100
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Subject: [PATCH 104/250] net: ethernet: mtk_eth_soc: convert clock bitmap to
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u64
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The to-be-added MT7988 SoC adds many new clocks which need to be
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controlled by the Ethernet driver, which will result in their total
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number exceeding 32.
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Prepare by converting clock bitmaps into 64-bit types.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Link: https://lore.kernel.org/r/6960a39bb0078cf84d7642a9558e6a91c6cc9df3.1690246066.git.daniel@makrotopia.org
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 96 +++++++++++----------
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1 file changed, 49 insertions(+), 47 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -663,54 +663,56 @@ enum mtk_clks_map {
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MTK_CLK_MAX
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};
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-#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
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- BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
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- BIT(MTK_CLK_TRGPLL))
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-#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
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- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
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- BIT(MTK_CLK_GP2) | \
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- BIT(MTK_CLK_SGMII_TX_250M) | \
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- BIT(MTK_CLK_SGMII_RX_250M) | \
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- BIT(MTK_CLK_SGMII_CDR_REF) | \
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- BIT(MTK_CLK_SGMII_CDR_FB) | \
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- BIT(MTK_CLK_SGMII_CK) | \
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- BIT(MTK_CLK_ETH2PLL))
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+#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
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+ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
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+ BIT_ULL(MTK_CLK_TRGPLL))
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+#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
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+ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
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+ BIT_ULL(MTK_CLK_GP2) | \
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+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
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+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
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+ BIT_ULL(MTK_CLK_SGMII_CK) | \
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+ BIT_ULL(MTK_CLK_ETH2PLL))
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#define MT7621_CLKS_BITMAP (0)
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#define MT7628_CLKS_BITMAP (0)
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-#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
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- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
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- BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
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- BIT(MTK_CLK_SGMII_TX_250M) | \
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- BIT(MTK_CLK_SGMII_RX_250M) | \
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- BIT(MTK_CLK_SGMII_CDR_REF) | \
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- BIT(MTK_CLK_SGMII_CDR_FB) | \
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- BIT(MTK_CLK_SGMII2_TX_250M) | \
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- BIT(MTK_CLK_SGMII2_RX_250M) | \
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- BIT(MTK_CLK_SGMII2_CDR_REF) | \
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- BIT(MTK_CLK_SGMII2_CDR_FB) | \
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- BIT(MTK_CLK_SGMII_CK) | \
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- BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
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-#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
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- BIT(MTK_CLK_WOCPU0) | \
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- BIT(MTK_CLK_SGMII_TX_250M) | \
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- BIT(MTK_CLK_SGMII_RX_250M) | \
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- BIT(MTK_CLK_SGMII_CDR_REF) | \
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- BIT(MTK_CLK_SGMII_CDR_FB) | \
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- BIT(MTK_CLK_SGMII2_TX_250M) | \
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- BIT(MTK_CLK_SGMII2_RX_250M) | \
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- BIT(MTK_CLK_SGMII2_CDR_REF) | \
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- BIT(MTK_CLK_SGMII2_CDR_FB) | \
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- BIT(MTK_CLK_SGMII_CK))
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-#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
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- BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
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- BIT(MTK_CLK_SGMII_TX_250M) | \
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- BIT(MTK_CLK_SGMII_RX_250M) | \
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- BIT(MTK_CLK_SGMII_CDR_REF) | \
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- BIT(MTK_CLK_SGMII_CDR_FB) | \
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- BIT(MTK_CLK_SGMII2_TX_250M) | \
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- BIT(MTK_CLK_SGMII2_RX_250M) | \
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- BIT(MTK_CLK_SGMII2_CDR_REF) | \
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- BIT(MTK_CLK_SGMII2_CDR_FB))
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+#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
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+ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
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+ BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
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+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
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+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
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+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
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+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
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+ BIT_ULL(MTK_CLK_SGMII_CK) | \
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+ BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
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+#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
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+ BIT_ULL(MTK_CLK_GP1) | \
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+ BIT_ULL(MTK_CLK_WOCPU0) | \
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+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
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+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
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+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
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+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
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+ BIT_ULL(MTK_CLK_SGMII_CK))
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+#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
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+ BIT_ULL(MTK_CLK_GP1) | \
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+ BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
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+ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
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+ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
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+ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
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+ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
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+ BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
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enum mtk_dev_state {
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MTK_HW_INIT,
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@@ -1043,7 +1045,7 @@ struct mtk_soc_data {
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const struct mtk_reg_map *reg_map;
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u32 ana_rgc3;
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u64 caps;
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- u32 required_clks;
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+ u64 required_clks;
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bool required_pctl;
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u8 offload_version;
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u8 hash_offset;
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