forked from Openwrt/openwrt
9a038e7fd1
Copy config and patches from kernel 5.10 to kernel 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
128 lines
3.8 KiB
Diff
128 lines
3.8 KiB
Diff
From 6c43809bf1bee76c434e365a26546a92a5fbec14 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Thu, 14 Oct 2021 00:39:08 +0200
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Subject: net: dsa: qca8k: add support for sgmii falling edge
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Add support for this in the qca8k driver. Also add support for SGMII
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rx/tx clock falling edge. This is only present for pad0, pad5 and
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pad6 have these bit reserved from Documentation. Add a comment that this
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is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and
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setting falling in port0 applies to both configuration with sgmii used
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for port0 or port6.
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Co-developed-by: Matthew Hagan <mnhagan88@gmail.com>
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Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++
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drivers/net/dsa/qca8k.h | 4 ++++
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2 files changed, 67 insertions(+)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -978,6 +978,42 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri
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}
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static int
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+qca8k_parse_port_config(struct qca8k_priv *priv)
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+{
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+ struct device_node *port_dn;
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+ phy_interface_t mode;
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+ struct dsa_port *dp;
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+ int port, ret;
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+
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+ /* We have 2 CPU port. Check them */
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+ for (port = 0; port < QCA8K_NUM_PORTS; port++) {
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+ /* Skip every other port */
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+ if (port != 0 && port != 6)
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+ continue;
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+
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+ dp = dsa_to_port(priv->ds, port);
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+ port_dn = dp->dn;
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+
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+ if (!of_device_is_available(port_dn))
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+ continue;
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+
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+ ret = of_get_phy_mode(port_dn, &mode);
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+ if (ret)
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+ continue;
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+
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+ if (mode == PHY_INTERFACE_MODE_SGMII) {
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+ if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
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+ priv->sgmii_tx_clk_falling_edge = true;
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+
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+ if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
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+ priv->sgmii_rx_clk_falling_edge = true;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static int
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qca8k_setup(struct dsa_switch *ds)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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@@ -990,6 +1026,11 @@ qca8k_setup(struct dsa_switch *ds)
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return -EINVAL;
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}
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+ /* Parse CPU port config to be later used in phy_link mac_config */
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+ ret = qca8k_parse_port_config(priv);
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+ if (ret)
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+ return ret;
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+
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mutex_init(&priv->reg_mutex);
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/* Start by setting up the register mapping */
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@@ -1274,6 +1315,28 @@ qca8k_phylink_mac_config(struct dsa_swit
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}
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qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
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+
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+ /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
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+ * falling edge is set writing in the PORT0 PAD reg
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+ */
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+ if (priv->switch_id == QCA8K_ID_QCA8327 ||
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+ priv->switch_id == QCA8K_ID_QCA8337)
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+ reg = QCA8K_REG_PORT0_PAD_CTRL;
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+
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+ val = 0;
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+
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+ /* SGMII Clock phase configuration */
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+ if (priv->sgmii_rx_clk_falling_edge)
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+ val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
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+
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+ if (priv->sgmii_tx_clk_falling_edge)
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+ val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
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+
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+ if (val)
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+ ret = qca8k_rmw(priv, reg,
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+ QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
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+ QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
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+ val);
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break;
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default:
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dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -35,6 +35,8 @@
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#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
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#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
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#define QCA8K_REG_PORT0_PAD_CTRL 0x004
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+#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
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+#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18)
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#define QCA8K_REG_PORT5_PAD_CTRL 0x008
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#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
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#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
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@@ -260,6 +262,8 @@ struct qca8k_priv {
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u8 switch_revision;
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u8 rgmii_tx_delay;
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u8 rgmii_rx_delay;
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+ bool sgmii_rx_clk_falling_edge;
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+ bool sgmii_tx_clk_falling_edge;
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bool legacy_phy_port_mapping;
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struct regmap *regmap;
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struct mii_bus *bus;
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