forked from Openwrt/openwrt
100 lines
3.8 KiB
Diff
100 lines
3.8 KiB
Diff
From 5e61fe157a27afc7c0d4f7bcbceefdca536c015f Mon Sep 17 00:00:00 2001
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From: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Date: Wed, 17 Aug 2022 14:32:52 +0200
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Subject: [PATCH] net: phy: Introduce QUSGMII PHY mode
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The QUSGMII mode is a derivative of Cisco's USXGMII standard. This
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standard is pretty similar to SGMII, but allows for faster speeds, and
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has the build-in bits for Quad and Octa variants (like QSGMII).
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The main difference with SGMII/QSGMII is that USXGMII/QUSGMII re-uses
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the preamble to carry various information, named 'Extensions'.
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As of today, the USXGMII standard only mentions the "PCH" extension,
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which is used to convey timestamps, allowing in-band signaling of PTP
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timestamps without having to modify the frame itself.
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This commit adds support for that mode. When no extension is in use, it
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behaves exactly like QSGMII, although it's not compatible with QSGMII.
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Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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Documentation/networking/phy.rst | 9 +++++++++
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drivers/net/phy/phylink.c | 3 +++
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include/linux/phy.h | 4 ++++
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3 files changed, 16 insertions(+)
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--- a/Documentation/networking/phy.rst
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+++ b/Documentation/networking/phy.rst
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@@ -303,6 +303,15 @@ Some of the interface modes are describe
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rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
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data rate of 100Mpbs.
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+``PHY_INTERFACE_MODE_QUSGMII``
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+ This defines the Cisco the Quad USGMII mode, which is the Quad variant of
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+ the USGMII (Universal SGMII) link. It's very similar to QSGMII, but uses
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+ a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not
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+ only the port id, but also so-called "extensions". The only documented
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+ extension so-far in the specification is the inclusion of timestamps, for
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+ PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
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+ same capabilities in terms of link speed and negociation.
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+
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Pause frames / flow control
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===========================
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--- a/drivers/net/phy/phylink.c
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+++ b/drivers/net/phy/phylink.c
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@@ -367,6 +367,7 @@ void phylink_get_linkmodes(unsigned long
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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+ case PHY_INTERFACE_MODE_QUSGMII:
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_GMII:
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caps |= MAC_1000HD | MAC_1000FD;
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@@ -630,6 +631,7 @@ static int phylink_parse_mode(struct phy
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switch (pl->link_config.interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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+ case PHY_INTERFACE_MODE_QUSGMII:
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phylink_set(pl->supported, 10baseT_Half);
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phylink_set(pl->supported, 10baseT_Full);
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phylink_set(pl->supported, 100baseT_Half);
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@@ -2956,6 +2958,7 @@ void phylink_mii_c22_pcs_get_state(struc
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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+ case PHY_INTERFACE_MODE_QUSGMII:
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phylink_decode_sgmii_word(state, lpa);
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break;
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--- a/include/linux/phy.h
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+++ b/include/linux/phy.h
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@@ -115,6 +115,7 @@ extern const int phy_10gbit_features_arr
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* @PHY_INTERFACE_MODE_25GBASER: 25G BaseR
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* @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII
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* @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
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+ * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
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* @PHY_INTERFACE_MODE_MAX: Book keeping
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*
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* Describes the interface between the MAC and PHY.
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@@ -152,6 +153,7 @@ typedef enum {
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PHY_INTERFACE_MODE_USXGMII,
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/* 10GBASE-KR - with Clause 73 AN */
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PHY_INTERFACE_MODE_10GKR,
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+ PHY_INTERFACE_MODE_QUSGMII,
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PHY_INTERFACE_MODE_MAX,
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} phy_interface_t;
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@@ -267,6 +269,8 @@ static inline const char *phy_modes(phy_
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return "10gbase-kr";
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case PHY_INTERFACE_MODE_100BASEX:
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return "100base-x";
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+ case PHY_INTERFACE_MODE_QUSGMII:
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+ return "qusgmii";
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default:
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return "unknown";
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}
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