forked from Openwrt/openwrt
ee035de0fd
Import patches from Linux v5.16 and v5.17 to get 2500Base-X SFP working
again with mvneta driver after the generic phylink validate backport.
Fixes: aab466f422 ("kernel: backport generic phylink validate")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
49 lines
1.9 KiB
Diff
49 lines
1.9 KiB
Diff
From fdedb695e6a8657302341cda81d519ef04f9acaa Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@armlinux.org.uk>
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Date: Wed, 27 Oct 2021 10:03:43 +0100
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Subject: [PATCH] net: mvneta: populate supported_interfaces member
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Populate the phy_interface_t bitmap for the Marvell mvneta driver with
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interfaces modes supported by the MAC.
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/marvell/mvneta.c | 25 +++++++++++++++++++++++++
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1 file changed, 25 insertions(+)
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--- a/drivers/net/ethernet/marvell/mvneta.c
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+++ b/drivers/net/ethernet/marvell/mvneta.c
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@@ -5180,6 +5180,31 @@ static int mvneta_probe(struct platform_
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pp->phylink_config.dev = &dev->dev;
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pp->phylink_config.type = PHYLINK_NETDEV;
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+ phy_interface_set_rgmii(pp->phylink_config.supported_interfaces);
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+ __set_bit(PHY_INTERFACE_MODE_QSGMII,
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+ pp->phylink_config.supported_interfaces);
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+ if (comphy) {
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+ /* If a COMPHY is present, we can support any of the serdes
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+ * modes and switch between them.
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+ */
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+ __set_bit(PHY_INTERFACE_MODE_SGMII,
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+ pp->phylink_config.supported_interfaces);
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+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
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+ pp->phylink_config.supported_interfaces);
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+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
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+ pp->phylink_config.supported_interfaces);
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+ } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
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+ /* No COMPHY, with only 2500BASE-X mode supported */
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+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
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+ pp->phylink_config.supported_interfaces);
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+ } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
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+ phy_mode == PHY_INTERFACE_MODE_SGMII) {
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+ /* No COMPHY, we can switch between 1000BASE-X and SGMII */
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+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
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+ pp->phylink_config.supported_interfaces);
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+ __set_bit(PHY_INTERFACE_MODE_SGMII,
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+ pp->phylink_config.supported_interfaces);
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+ }
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phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode,
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phy_mode, &mvneta_phylink_ops);
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