forked from Openwrt/openwrt
8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
109 lines
2.9 KiB
Diff
109 lines
2.9 KiB
Diff
From fd553e002cb908f0dd681af0b3ddb62965e0cc41 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Mon, 6 May 2024 12:21:21 +0100
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Subject: [PATCH 1077/1085] overlays: Add sc16is750-spi0
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Essentially a rename of the equivalent overlay for the SC16IS752.
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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arch/arm/boot/dts/overlays/Makefile | 1 +
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arch/arm/boot/dts/overlays/README | 8 +++
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.../dts/overlays/sc16is750-spi0-overlay.dts | 63 +++++++++++++++++++
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3 files changed, 72 insertions(+)
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create mode 100644 arch/arm/boot/dts/overlays/sc16is750-spi0-overlay.dts
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--- a/arch/arm/boot/dts/overlays/Makefile
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+++ b/arch/arm/boot/dts/overlays/Makefile
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@@ -230,6 +230,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
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rra-digidac1-wm8741-audio.dtbo \
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sainsmart18.dtbo \
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sc16is750-i2c.dtbo \
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+ sc16is750-spi0.dtbo \
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sc16is752-i2c.dtbo \
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sc16is752-spi0.dtbo \
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sc16is752-spi1.dtbo \
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--- a/arch/arm/boot/dts/overlays/README
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+++ b/arch/arm/boot/dts/overlays/README
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@@ -4128,6 +4128,14 @@ Params: int_pin GPIO use
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xtal On-board crystal frequency (default 14745600)
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+Name: sc16is750-spi0
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+Info: Overlay for the NXP SC16IS750 UART with SPI Interface
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+ Enables the chip on SPI0.
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+Load: dtoverlay=sc16is750-spi0,<param>=<val>
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+Params: int_pin GPIO used for IRQ (default 24)
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+ xtal On-board crystal frequency (default 14745600)
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+
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+
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Name: sc16is752-i2c
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Info: Overlay for the NXP SC16IS752 dual UART with I2C Interface
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Enables the chip on I2C1 at 0x48 (or the "addr" parameter value). To
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlays/sc16is750-spi0-overlay.dts
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@@ -0,0 +1,63 @@
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "brcm,bcm2835";
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+
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+ fragment@0 {
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+ target = <&spi0>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "okay";
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+
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+ sc16is750: sc16is750@0 {
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+ compatible = "nxp,sc16is750";
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+ reg = <0>; /* CE0 */
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+ clocks = <&sc16is750_clk>;
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+ interrupt-parent = <&gpio>;
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+ interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */
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+ pinctrl-0 = <&int_pins>;
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+ pinctrl-names = "default";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ spi-max-frequency = <4000000>;
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+ };
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&spidev0>;
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+ __overlay__ {
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+ status = "disabled";
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+ };
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+ };
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+
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+ fragment@2 {
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+ target-path = "/";
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+ __overlay__ {
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+ sc16is750_clk: sc16is750_spi0_0_clk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <14745600>;
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+ };
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+ };
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+ };
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+
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+ fragment@3 {
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+ target = <&gpio>;
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+ __overlay__ {
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+ int_pins: int_pins@18 {
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+ brcm,pins = <24>;
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+ brcm,function = <0>; /* in */
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+ brcm,pull = <0>; /* none */
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+ };
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+ };
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+ };
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+
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+ __overrides__ {
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+ int_pin = <&sc16is750>,"interrupts:0", <&int_pins>,"brcm,pins:0",
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+ <&int_pins>,"reg:0";
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+ xtal = <&sc16is750_clk>,"clock-frequency:0";
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+ };
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+};
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