forked from Openwrt/openwrt
69dd5a788f
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.37 Added: generic/hack-6.6/900-fix-build-to-handle-return-value.patch[1] Manually rebased: generic/pending-6.6/834-ledtrig-libata.patch Removed upstreamed: bcm27xx/patches-6.6/950-0398-drm-panel-panel-ilitek9881c-Use-cansleep-methods.patch[2] All other patches automatically rebased. 1. Patch suggested by @DragonBluep to circumvent upstream breakage of kernel 6.6.37 compilation. See comments in https://github.com/openwrt/openwrt/pull/15879 for additional discussion. 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.37&id=1618f7a875ffd916596392fd29880c0429b8af60 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/15879 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
68 lines
2.3 KiB
Diff
68 lines
2.3 KiB
Diff
From 337caf7170e9cd721c0903c46e56bc05fb5b625d Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Wed, 20 Mar 2024 10:59:10 +0000
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Subject: [PATCH 0981/1085] drivers: sdhci-brcmstb: set CQE timer clock
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frequency
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CQHCI keeps track of tags in flight with internal timers, so the clock
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frequency driving the timer needs to be specified. The config registers
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default to 0 (100kHz) which means timeouts will be significantly shorter
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than they should be. Assume the timer clock comes from the controller
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base clock.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/mmc/host/sdhci-brcmstb.c | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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--- a/drivers/mmc/host/sdhci-brcmstb.c
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+++ b/drivers/mmc/host/sdhci-brcmstb.c
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@@ -42,6 +42,9 @@
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#define SDIO_CFG_SD_PIN_SEL_SD BIT(1)
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#define SDIO_CFG_SD_PIN_SEL_MMC BIT(0)
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+#define SDIO_CFG_CQ_CAPABILITY 0x4c
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+#define SDIO_CFG_CQ_CAPABILITY_FMUL_SHIFT 12
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+
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#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac
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#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31)
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#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0)
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@@ -202,7 +205,7 @@ static void sdhci_brcmstb_cfginit_2712(s
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u32 uhs_mask = (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104);
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u32 hsemmc_mask = (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR |
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MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V);
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- u32 reg;
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+ u32 reg, base_clk_mhz;
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/*
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* If we support a speed that requires tuning,
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@@ -223,6 +226,11 @@ static void sdhci_brcmstb_cfginit_2712(s
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reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN;
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writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
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}
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+
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+ /* Guesstimate the timer frequency (controller base clock) */
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+ base_clk_mhz = max_t(u32, clk_get_rate(pltfm_host->clk) / (1000 * 1000), 1);
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+ reg = (3 << SDIO_CFG_CQ_CAPABILITY_FMUL_SHIFT) | base_clk_mhz;
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+ writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CQ_CAPABILITY);
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}
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static int bcm2712_init_sd_express(struct sdhci_host *host, struct mmc_ios *ios)
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@@ -494,6 +502,8 @@ static int sdhci_brcmstb_probe(struct pl
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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+ pltfm_host->clk = clk;
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+
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priv = sdhci_pltfm_priv(pltfm_host);
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if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
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priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
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@@ -627,7 +637,6 @@ add_host:
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if (res)
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goto err;
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- pltfm_host->clk = clk;
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return res;
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err:
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