forked from Openwrt/openwrt
69dd5a788f
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.37 Added: generic/hack-6.6/900-fix-build-to-handle-return-value.patch[1] Manually rebased: generic/pending-6.6/834-ledtrig-libata.patch Removed upstreamed: bcm27xx/patches-6.6/950-0398-drm-panel-panel-ilitek9881c-Use-cansleep-methods.patch[2] All other patches automatically rebased. 1. Patch suggested by @DragonBluep to circumvent upstream breakage of kernel 6.6.37 compilation. See comments in https://github.com/openwrt/openwrt/pull/15879 for additional discussion. 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.37&id=1618f7a875ffd916596392fd29880c0429b8af60 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/15879 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
127 lines
4.2 KiB
Diff
127 lines
4.2 KiB
Diff
From c6187bb277ed61836b3dd6da913d2a6d107f93e4 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Fri, 9 Feb 2024 13:47:23 +0000
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Subject: [PATCH 0891/1085] drivers: mmc: sdhci-brcmstb: fix usage of
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SD_PIN_SEL on BCM2712
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The SDIO_CFG register SD_PIN_SEL conflates two settings - whether eMMC
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HS or SD UHS timings are applied to the interface, and whether or not
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the card-detect line is functional. SD_PIN_SEL can only be changed when
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the SD clock isn't running, so add a bcm2712-specific clock setup.
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Toggling SD_PIN_SEL at runtime means the integrated card-detect feature
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can't be used, so this controller needs a cd-gpios property.
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Also fix conditionals for usage of the delay-line PHY - no-1-8-v will
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imply no bits set in hsemmc_mask or uhs_mask, so remove it.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/mmc/host/sdhci-brcmstb.c | 61 ++++++++++++++++++++++----------
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1 file changed, 43 insertions(+), 18 deletions(-)
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--- a/drivers/mmc/host/sdhci-brcmstb.c
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+++ b/drivers/mmc/host/sdhci-brcmstb.c
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@@ -39,7 +39,8 @@
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#define SDIO_CFG_SD_PIN_SEL 0x44
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#define SDIO_CFG_SD_PIN_SEL_MASK 0x3
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-#define SDIO_CFG_SD_PIN_SEL_CARD BIT(1)
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+#define SDIO_CFG_SD_PIN_SEL_SD BIT(1)
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+#define SDIO_CFG_SD_PIN_SEL_MMC BIT(0)
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#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac
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#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31)
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@@ -103,6 +104,42 @@ static void sdhci_brcmstb_hs400es(struct
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writel(reg, host->ioaddr + SDHCI_VENDOR);
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}
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+static void sdhci_bcm2712_set_clock(struct sdhci_host *host, unsigned int clock)
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+{
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+ u16 clk;
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+ u32 reg;
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+ bool is_emmc_rate = false;
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+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+ struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
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+
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+ host->mmc->actual_clock = 0;
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+
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+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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+
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+ switch (host->mmc->ios.timing) {
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+ case MMC_TIMING_MMC_HS400:
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+ case MMC_TIMING_MMC_HS200:
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+ case MMC_TIMING_MMC_DDR52:
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+ case MMC_TIMING_MMC_HS:
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+ is_emmc_rate = true;
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+ break;
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+ }
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+
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+ reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL);
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+ reg &= ~SDIO_CFG_SD_PIN_SEL_MASK;
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+ if (is_emmc_rate)
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+ reg |= SDIO_CFG_SD_PIN_SEL_MMC;
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+ else
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+ reg |= SDIO_CFG_SD_PIN_SEL_SD;
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+ writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL);
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+
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+ if (clock == 0)
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+ return;
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+
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+ clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
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+ sdhci_enable_clk(host, clk);
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+}
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+
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static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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u16 clk;
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@@ -162,22 +199,16 @@ static void sdhci_brcmstb_cfginit_2712(s
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
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- bool want_dll = false;
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u32 uhs_mask = (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104);
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u32 hsemmc_mask = (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR |
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MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V);
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u32 reg;
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- if (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)) {
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- if((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask))
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- want_dll = true;
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- }
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-
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/*
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- * If we want a speed that requires tuning,
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- * then select the delay line PHY as the clock source.
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- */
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- if (want_dll) {
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+ * If we support a speed that requires tuning,
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+ * then select the delay line PHY as the clock source.
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+ */
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+ if ((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask)) {
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reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
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reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE;
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reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE;
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@@ -191,12 +222,6 @@ static void sdhci_brcmstb_cfginit_2712(s
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reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV;
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reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN;
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writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
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- } else {
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- /* Enable card detection line */
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- reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL);
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- reg &= ~SDIO_CFG_SD_PIN_SEL_MASK;
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- reg |= SDIO_CFG_SD_PIN_SEL_CARD;
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- writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL);
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}
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}
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@@ -331,7 +356,7 @@ static struct sdhci_ops sdhci_brcmstb_op
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};
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static struct sdhci_ops sdhci_brcmstb_ops_2712 = {
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- .set_clock = sdhci_set_clock,
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+ .set_clock = sdhci_bcm2712_set_clock,
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.set_power = sdhci_brcmstb_set_power,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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