forked from Openwrt/openwrt
8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
156 lines
5.3 KiB
Diff
156 lines
5.3 KiB
Diff
From a4f577bc6a231542ed348fec6d2c00d813a411cd Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Mon, 25 Sep 2023 16:57:07 +0100
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Subject: [PATCH 0598/1085] drm/vc4: Move the buffer offset out of the
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vc4_plane_state
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The offset fields in vc4_plane_state are described as being
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the offset for each buffer in the bo, however it is used to
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store the complete DMA address that is then written into the
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register.
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The DMA address including the fb ofset can be retrieved
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using drm_fb_dma_get_gem_addr, and the offset adjustment due to
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clipping is local to vc4_plane_mode_set.
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Drop the offset field from the state, and compute the complete
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DMA address in vc4_plane_mode_set.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_drv.h | 5 ----
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drivers/gpu/drm/vc4/vc4_plane.c | 51 +++++++++++++--------------------
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2 files changed, 20 insertions(+), 36 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -431,11 +431,6 @@ struct vc4_plane_state {
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bool is_unity;
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bool is_yuv;
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- /* Offset to start scanning out from the start of the plane's
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- * BO.
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- */
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- u32 offsets[3];
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-
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/* Our allocation in LBM for temporary storage during scaling. */
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struct drm_mm_node lbm;
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -450,12 +450,11 @@ static int vc4_plane_setup_clipping_and_
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{
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struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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struct drm_framebuffer *fb = state->fb;
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- struct drm_gem_dma_object *bo;
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int num_planes = fb->format->num_planes;
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struct drm_crtc_state *crtc_state;
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u32 h_subsample = fb->format->hsub;
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u32 v_subsample = fb->format->vsub;
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- int i, ret;
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+ int ret;
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crtc_state = drm_atomic_get_existing_crtc_state(state->state,
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state->crtc);
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@@ -469,11 +468,6 @@ static int vc4_plane_setup_clipping_and_
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if (ret)
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return ret;
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- for (i = 0; i < num_planes; i++) {
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- bo = drm_fb_dma_get_gem_obj(fb, i);
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- vc4_state->offsets[i] = bo->dma_addr + fb->offsets[i];
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- }
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-
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vc4_state->src_x = state->src.x1;
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vc4_state->src_y = state->src.y1;
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vc4_state->src_w[0] = state->src.x2 - vc4_state->src_x;
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@@ -896,6 +890,7 @@ static int vc4_plane_mode_set(struct drm
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u32 width, height;
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u32 hvs_format = format->hvs;
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unsigned int rotation;
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+ u32 offsets[3] = { 0 };
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int ret, i;
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if (vc4_state->dlist_initialized)
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@@ -943,13 +938,8 @@ static int vc4_plane_mode_set(struct drm
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* out.
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*/
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for (i = 0; i < num_planes; i++) {
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- vc4_state->offsets[i] += src_y /
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- (i ? v_subsample : 1) *
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- fb->pitches[i];
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-
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- vc4_state->offsets[i] += src_x /
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- (i ? h_subsample : 1) *
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- fb->format->cpp[i];
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+ offsets[i] += src_y / (i ? v_subsample : 1) * fb->pitches[i];
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+ offsets[i] += src_x / (i ? h_subsample : 1) * fb->format->cpp[i];
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}
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break;
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@@ -1004,19 +994,18 @@ static int vc4_plane_mode_set(struct drm
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VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
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VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
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VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
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- vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
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- vc4_state->offsets[0] += subtile_y << 8;
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- vc4_state->offsets[0] += utile_y << 4;
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+ offsets[0] += tiles_t * (tiles_w << tile_size_shift);
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+ offsets[0] += subtile_y << 8;
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+ offsets[0] += utile_y << 4;
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/* Rows of tiles alternate left-to-right and right-to-left. */
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if (tiles_t & 1) {
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pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
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- vc4_state->offsets[0] += (tiles_w - tiles_l) <<
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- tile_size_shift;
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- vc4_state->offsets[0] -= (1 + !tile_y) << 10;
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+ offsets[0] += (tiles_w - tiles_l) << tile_size_shift;
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+ offsets[0] -= (1 + !tile_y) << 10;
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} else {
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- vc4_state->offsets[0] += tiles_l << tile_size_shift;
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- vc4_state->offsets[0] += tile_y << 10;
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+ offsets[0] += tiles_l << tile_size_shift;
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+ offsets[0] += tile_y << 10;
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}
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break;
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@@ -1105,11 +1094,9 @@ static int vc4_plane_mode_set(struct drm
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tile = src_x / pix_per_tile;
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- vc4_state->offsets[i] += param * tile_w * tile;
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- vc4_state->offsets[i] += src_y /
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- (i ? v_subsample : 1) *
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- tile_w;
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- vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
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+ offsets[i] += param * tile_w * tile;
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+ offsets[i] += src_y / (i ? v_subsample : 1) * tile_w;
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+ offsets[i] += x_off & ~(i ? 1 : 0);
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}
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pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
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@@ -1253,8 +1240,12 @@ static int vc4_plane_mode_set(struct drm
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* The pointers may be any byte address.
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*/
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vc4_state->ptr0_offset[0] = vc4_state->dlist_count;
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- for (i = 0; i < num_planes; i++)
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- vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
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+
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+ for (i = 0; i < num_planes; i++) {
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+ dma_addr_t paddr = drm_fb_dma_get_gem_addr(fb, state, i);
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+
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+ vc4_dlist_write(vc4_state, paddr + offsets[i]);
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+ }
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/* Pointer Context Word 0/1/2: Written by the HVS */
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for (i = 0; i < num_planes; i++)
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@@ -1517,8 +1508,6 @@ static void vc4_plane_atomic_async_updat
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sizeof(vc4_state->y_scaling));
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vc4_state->is_unity = new_vc4_state->is_unity;
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vc4_state->is_yuv = new_vc4_state->is_yuv;
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- memcpy(vc4_state->offsets, new_vc4_state->offsets,
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- sizeof(vc4_state->offsets));
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vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
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/* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
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