forked from Openwrt/openwrt
8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
106 lines
3.7 KiB
Diff
106 lines
3.7 KiB
Diff
From 082526e9709190ec5e035266a33a7a4858ad7a79 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Fri, 9 Apr 2021 15:00:40 +0100
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Subject: [PATCH 0021/1085] vc4/drm: Handle fractional coordinates using the
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phase field
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 61 ++++++++++++++++++++++++++++++---
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1 file changed, 56 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -532,14 +532,47 @@ static void vc4_write_tpz(struct vc4_pla
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VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
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}
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-static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
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+/* phase magnitude bits */
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+#define PHASE_BITS 6
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+
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+static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst, u32 xy, int channel)
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{
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- u32 scale = (1 << 16) * src / dst;
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+ u32 scale = src / dst;
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+ s32 offset, offset2;
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+ s32 phase;
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+
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+ /* Start the phase at 1/2 pixel from the 1st pixel at src_x.
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+ 1/4 pixel for YUV. */
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+ if (channel) {
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+ /* the phase is relative to scale_src->x, so shift it for display list's x value */
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+ offset = (xy & 0x1ffff) >> (16 - PHASE_BITS) >> 1;
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+ offset += -(1 << PHASE_BITS >> 2);
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+ } else {
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+ /* the phase is relative to scale_src->x, so shift it for display list's x value */
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+ offset = (xy & 0xffff) >> (16 - PHASE_BITS);
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+ offset += -(1 << PHASE_BITS >> 1);
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+
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+ /* This is a kludge to make sure the scaling factors are consitent with YUV's luma scaling.
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+ we lose 1bit precision because of this. */
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+ scale &= ~1;
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+ }
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+
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+ /* There may be a also small error introduced by precision of scale.
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+ Add half of that as a compromise */
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+ offset2 = src - dst * scale;
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+ offset2 >>= 16 - PHASE_BITS;
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+ phase = offset + (offset2 >> 1);
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+
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+ /* Ensure +ve values don't touch the sign bit, then truncate negative values */
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+ if (phase >= 1 << PHASE_BITS)
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+ phase = (1 << PHASE_BITS) - 1;
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+
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+ phase &= SCALER_PPF_IPHASE_MASK;
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vc4_dlist_write(vc4_state,
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SCALER_PPF_AGC |
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VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
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- VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
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+ VC4_SET_FIELD(phase, SCALER_PPF_IPHASE));
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}
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static u32 vc4_lbm_size(struct drm_plane_state *state)
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@@ -598,13 +631,13 @@ static void vc4_write_scaling_parameters
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/* Ch0 H-PPF Word 0: Scaling Parameters */
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if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
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vc4_write_ppf(vc4_state,
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- vc4_state->src_w[channel], vc4_state->crtc_w);
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+ vc4_state->src_w[channel], vc4_state->crtc_w, vc4_state->src_x, channel);
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}
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/* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
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if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
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vc4_write_ppf(vc4_state,
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- vc4_state->src_h[channel], vc4_state->crtc_h);
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+ vc4_state->src_h[channel], vc4_state->crtc_h, vc4_state->src_y, channel);
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vc4_dlist_write(vc4_state, 0xc0c0c0c0);
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}
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@@ -1052,6 +1085,24 @@ static int vc4_plane_mode_set(struct drm
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return -EINVAL;
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}
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+ /* fetch an extra pixel if we don't actually line up with the left edge. */
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+ if ((vc4_state->src_x & 0xffff) && vc4_state->src_x < (state->fb->width << 16))
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+ width++;
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+
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+ /* same for the right side */
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+ if (((vc4_state->src_x + vc4_state->src_w[0]) & 0xffff) &&
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+ vc4_state->src_x + vc4_state->src_w[0] < (state->fb->width << 16))
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+ width++;
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+
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+ /* now for the top */
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+ if ((vc4_state->src_y & 0xffff) && vc4_state->src_y < (state->fb->height << 16))
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+ height++;
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+
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+ /* and the bottom */
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+ if (((vc4_state->src_y + vc4_state->src_h[0]) & 0xffff) &&
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+ vc4_state->src_y + vc4_state->src_h[0] < (state->fb->height << 16))
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+ height++;
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+
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/* Don't waste cycles mixing with plane alpha if the set alpha
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* is opaque or there is no per-pixel alpha information.
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* In any case we use the alpha property value as the fixed alpha.
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