c196398c44
similar to mv_sata, use nr-ports attribute from device tree. import and adapt locking code from vendor GPL sources. add dma controller handling, it may be used in future to avoid full core resets similar to the vendor SDK's "progressive cleanup" function. this is still very dirty and aimed to first of all do things quite exactly like the reference code. and it somehow works. obviously there is lots of room for improvement :) Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43598
344 lines
8.9 KiB
Plaintext
344 lines
8.9 KiB
Plaintext
/*
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* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "plxtech,nas7820", "plxtech,nas782x";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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/* alias to determine bank index */
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gpio0 = &GPIOA;
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gpio1 = &GPIOB;
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ethernet0 = &gmac;
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};
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cpus {
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cpu@0 {
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compatible = "arm,arm11mpcore";
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};
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cpu@1 {
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compatible = "arm,arm11mpcore";
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};
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};
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gic: gic@47001000 {
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compatible = "arm,arm11mp-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x47001000 0x1000>,
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<0x47000100 0x0100>;
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};
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rst: reset-controller@44E00034 {
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compatible = "plxtech,nas782x-reset";
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#reset-cells = <1>;
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reg = <0x44E00034 0x8>; /* currently not used */
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};
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rps: rps@44400000 {
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compatible = "plxtech,nas782x-rps";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x44400000 0x14>;
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interrupts = <0 5 0x304>;
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};
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/* external oscillator */
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osc: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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sysclk: sysclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&osc>;
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};
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plla: plla@44e001f0 {
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compatible = "plxtech,nas782x-plla";
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#clock-cells = <0>;
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clocks = <&osc>;
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reg = <0x44e001f0 0x10>;
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};
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pllb: pllb@44f001f0 {
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compatible = "plxtech,nas782x-pllb";
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#clock-cells = <0>;
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clocks = <&osc>;
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reg = <0x44f001f0 0x10>;
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resets = <&rst 31>;
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};
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stdclk: stdclk {
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compatible = "plxtech,nas782x-stdclk";
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#clock-cells = <1>;
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clocks = <&osc>;
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};
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twdclk: twdclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&plla>;
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};
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gmacclk: gmacclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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pinctrl {
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/* act as a simple bus, so children will be probed automatically */
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "plxtech,nas782x-pinctrl", "simple-bus";
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ranges;
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plxtech,mux-mask = <
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0xFFFFFFFF 0xCC0FFDF9 0xFC000E60 0x0F03F7E0 0xF00C0FE0
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0x0003FFFF 0x00037FFF 0x0003FFF8 0x00000F00 0x0003F7F3
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>;
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GPIOA: gpio@44000000 {
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compatible = "plxtech,nas782x-gpio";
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reg = <0x44000000 0x100>, <0x44E00000 0x200>;
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interrupts = <0 21 0x304>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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#gpio-lines = <32>; /* real gpio pin count */
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};
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GPIOB: gpio@44100000 {
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compatible = "plxtech,nas782x-gpio";
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reg = <0x44100000 0x100>, <0x44F00000 0x200>;
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interrupts = <0 22 0x304>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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#gpio-lines = <18>; /* real gpio pin count */
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};
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uart0 {
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pinctrl_uart0: uart0-0 {
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plxtech,pins =
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<0 30 5 0 /* MF_A30 PINMUX_ALT PINMUX_UARTA_SIN */
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0 31 5 0>; /* MF_A31 PINMUX_ALT PINMUX_UARTA_SOUT */
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};
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};
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gmac0 {
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pinctrl_gmac0: gmac0-0 {
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plxtech,pins =
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<0 3 1 0 /* MF_A3 PINMUX_2 PINMUX_MACA_MDC */
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0 4 1 0>; /* MF_A4 PINMUX_2 PINMUX_MACA_MDIO */
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};
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};
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nand0 {
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pinctrl_nand0: nand0-0 {
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plxtech,pins =
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<0 12 1 0 /* MF_A12 PINMUX_2 PINMUX_STATIC_DATA0 */
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0 13 1 0 /* MF_A13 PINMUX_2 PINMUX_STATIC_DATA1 */
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0 14 1 0 /* MF_A14 PINMUX_2 PINMUX_STATIC_DATA2 */
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0 15 1 0 /* MF_A15 PINMUX_2 PINMUX_STATIC_DATA3 */
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0 16 1 0 /* MF_A16 PINMUX_2 PINMUX_STATIC_DATA4 */
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0 17 1 0 /* MF_A17 PINMUX_2 PINMUX_STATIC_DATA5 */
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0 18 1 0 /* MF_A18 PINMUX_2 PINMUX_STATIC_DATA6 */
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0 19 1 0 /* MF_A19 PINMUX_2 PINMUX_STATIC_DATA7 */
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0 20 1 0 /* MF_A20 PINMUX_2 PINMUX_STATIC_NWE */
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0 21 1 0 /* MF_A21 PINMUX_2 PINMUX_STATIC_NOE */
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0 22 1 0 /* MF_A22 PINMUX_2 PINMUX_STATIC_NCS */
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0 23 1 0 /* MF_A23 PINMUX_2 PINMUX_STATIC_ADDR18 */
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0 24 1 0>; /* MF_A24 PINMUX_2 PINMUX_STATIC_ADDR19 */
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};
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};
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};
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pcie-controller@47C00000 {
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compatible = "plxtech,nas782x-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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/* flag & space bus address host address size */
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ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
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0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
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0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
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0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
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bus-range = <0x00 0x7f>;
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/* cfg inbound translator phy*/
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reg = <0x47C00000 0x1000>, <0x47D00000 0x100>, <0x44A00000 0x10>;
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#interrupt-cells = <1>;
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/* wild card mask, match all bus address & interrupt specifier */
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/* format: bus address mask, interrupt specifier mask */
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/* each bit 1 means need match, 0 means ignored when match */
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interrupt-map-mask = <0 0 0 0>;
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/* format: a list of: bus address, interrupt specifier,
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* parent interrupt controller & specifier */
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interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
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gpios = <&GPIOB 12 0>;
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clocks = <&stdclk 8>, <&pllb>;
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clock-names = "pcie", "busclk";
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resets = <&rst 7>, <&rst 14>;
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reset-names = "pcie", "phy";
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plxtech,pcie-hcsl-bit = <2>;
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plxtech,pcie-ctrl-offset = <0x120>;
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plxtech,pcie-outbound-offset = <0x138>;
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status = "disabled";
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};
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pcie-controller@47E00000 {
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compatible = "plxtech,nas782x-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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/* flag & space bus address host address size */
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ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
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0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
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0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
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0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
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bus-range = <0x80 0xff>;
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/* cfg inbound translator phy*/
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reg = <0x47E00000 0x1000>, <0x47F00000 0x100>, <0x44A00000 0x10>;
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#interrupt-cells = <1>;
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/* wild card mask, match all bus address & interrupt specifier */
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/* format: bus address mask, interrupt specifier mask */
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/* each bit 1 means need match, 0 means ignored when match */
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interrupt-map-mask = <0 0 0 0>;
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/* format: a list of: bus address, interrupt specifier,
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* parent interrupt controller & specifier */
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interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
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/* gpios = <&GPIOB 12 0>; */
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clocks = <&stdclk 11>, <&pllb>;
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clock-names = "pcie", "busclk";
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resets = <&rst 23>, <&rst 14>;
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reset-names = "pcie", "phy";
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plxtech,pcie-hcsl-bit = <3>;
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plxtech,pcie-ctrl-offset = <0x124>;
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plxtech,pcie-outbound-offset = <0x174>;
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status = "disabled";
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};
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local-timer@47000600 {
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compatible = "arm,arm11mp-twd-timer";
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reg = <0x47000600 0x20>;
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interrupts = <1 13 0x304>; /* percpu, irq 29, cpu mask 3, level high */
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clocks = <&twdclk>;
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};
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watchdog@47000620 {
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compatible = "mpcore_wdt";
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reg = <0x47000620 0x20>;
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interrupts = <1 14 0x304>; /* percpu, irq 30, cpu mask 3, level high */
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clocks = <&twdclk>;
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};
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timer@44400200 {
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compatible = "plxtech,nas782x-rps-timer";
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reg = <0x44400200 0x40>;
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clocks = <&sysclk>;
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};
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uart0: uart@44200000 {
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compatible = "ns16550a";
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reg = <0x44200000 0x100>;
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clock-frequency = <6250000>;
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interrupts = <0 23 0x304>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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status = "disabled";
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};
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sata@45900000 {
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compatible = "plxtech,nas782x-sata";
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/* ports dmactl sgdma */
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reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
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/* core phy descriptors (optional) */
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<0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
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interrupts = <0 18 0x304>;
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clocks = <&stdclk 4>;
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resets = <&rst 11>, <&rst 12>, <&rst 13>;
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reset-names = "sata", "link", "phy";
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nr-ports = <1>;
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status = "disabled";
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};
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nand@41000000 {
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compatible = "plxtech,nand-nas782x", "gen_nand";
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reg = <0x41000000 0x100000>, <0x41C00000 0x20>;
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nand-ecc-mode = "soft";
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clocks = <&stdclk 9>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand0>;
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resets = <&rst 15>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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gmac: ethernet@40400000 {
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compatible = "plxtech,nas782x-gmac", "snps,dwmac";
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reg = <0x40400000 0x2000>;
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interrupts = <0 8 0x304>, <0 17 0x304>;
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interrupt-names = "macirq", "eth_wake_irq";
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mac-address = [000000000000]; /* Filled in by U-Boot */
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phy-mode = "rgmii";
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clocks = <&stdclk 7>, <&gmacclk>;
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clock-names = "gmac", "stmmaceth";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gmac0>;
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resets = <&rst 6>;
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status = "disabled";
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};
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ehci@40200100 {
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compatible = "plxtech,nas782x-ehci";
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reg = <0x40200100 0xf00>;
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interrupts = <0 7 0x304>;
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clocks = <&stdclk 6>, <&pllb>, <&stdclk 12>;
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clock-names = "usb", "refsrc", "phyref";
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resets = <&rst 4>, <&rst 5>, <&rst 26>;
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reset-names = "host", "phya", "phyb";
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/* Otherwise ref300 is used, which is derived from sata phy
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* in that case, usb depends on sata initialization */
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/* FIXME: how to make this dependency explicit ? */
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plxtech,ehci_use_pllb;
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status = "disabled";
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};
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};
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