9ec72e7a42
This change set enables frequency scaling on ipq806x, which speeds-up the CPU and allows it to achieve its max frequency. These patches are cherry-picked & backported from the following location: *130-132: linux-next *133-143: LKML - https://lkml.org/lkml/2015/3/21/15 *144: derived from other qcom similar dts *145: derived from https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.14/drivers/cpufreq/cpufreq-krait.c Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 45730
128 lines
3.3 KiB
Diff
128 lines
3.3 KiB
Diff
Content-Type: text/plain; charset="utf-8"
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Subject: [v3,08/13] clk: qcom: Add IPQ806X's HFPLLs
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From: Stephen Boyd <sboyd@codeaurora.org>
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X-Patchwork-Id: 6063241
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Message-Id: <1426920332-9340-9-git-send-email-sboyd@codeaurora.org>
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To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
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Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
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linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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Viresh Kumar <viresh.kumar@linaro.org>
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Date: Fri, 20 Mar 2015 23:45:27 -0700
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Describe the HFPLLs present on IPQ806X devices.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 83 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -30,6 +30,7 @@
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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+#include "clk-hfpll.h"
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#include "reset.h"
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static struct clk_pll pll0 = {
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@@ -102,6 +103,85 @@ static struct clk_regmap pll8_vote = {
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},
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};
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+static struct hfpll_data hfpll0_data = {
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+ .mode_reg = 0x3200,
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+ .l_reg = 0x3208,
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+ .m_reg = 0x320c,
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+ .n_reg = 0x3210,
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+ .config_reg = 0x3204,
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+ .status_reg = 0x321c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3214,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll0 = {
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+ .d = &hfpll0_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll0",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
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+};
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+
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+static struct hfpll_data hfpll1_data = {
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+ .mode_reg = 0x3240,
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+ .l_reg = 0x3248,
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+ .m_reg = 0x324c,
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+ .n_reg = 0x3250,
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+ .config_reg = 0x3244,
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+ .status_reg = 0x325c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll1 = {
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+ .d = &hfpll1_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll1",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
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+};
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+
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+static struct hfpll_data hfpll_l2_data = {
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+ .mode_reg = 0x3300,
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+ .l_reg = 0x3308,
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+ .m_reg = 0x330c,
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+ .n_reg = 0x3310,
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+ .config_reg = 0x3304,
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+ .status_reg = 0x331c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll_l2 = {
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+ .d = &hfpll_l2_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll_l2",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
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+};
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+
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+
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static struct clk_pll pll14 = {
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.l_reg = 0x31c4,
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.m_reg = 0x31c8,
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@@ -2261,6 +2341,9 @@ static struct clk_regmap *gcc_ipq806x_cl
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[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
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[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
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[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
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+ [PLL9] = &hfpll0.clkr,
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+ [PLL10] = &hfpll1.clkr,
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+ [PLL12] = &hfpll_l2.clkr,
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};
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static const struct qcom_reset_map gcc_ipq806x_resets[] = {
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