358 lines
13 KiB
C
358 lines
13 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __mvCesaRegs_h__
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#define __mvCesaRegs_h__
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#include "mvTypes.h"
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typedef struct
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{
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/* word 0 */
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MV_U32 config;
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/* word 1 */
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MV_U16 cryptoSrcOffset;
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MV_U16 cryptoDstOffset;
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/* word 2 */
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MV_U16 cryptoDataLen;
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MV_U16 reserved1;
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/* word 3 */
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MV_U16 cryptoKeyOffset;
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MV_U16 reserved2;
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/* word 4 */
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MV_U16 cryptoIvOffset;
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MV_U16 cryptoIvBufOffset;
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/* word 5 */
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MV_U16 macSrcOffset;
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MV_U16 macTotalLen;
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/* word 6 */
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MV_U16 macDigestOffset;
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MV_U16 macDataLen;
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/* word 7 */
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MV_U16 macInnerIvOffset;
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MV_U16 macOuterIvOffset;
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} MV_CESA_DESC;
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/* operation */
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typedef enum
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{
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MV_CESA_MAC_ONLY = 0,
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MV_CESA_CRYPTO_ONLY = 1,
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MV_CESA_MAC_THEN_CRYPTO = 2,
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MV_CESA_CRYPTO_THEN_MAC = 3,
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MV_CESA_MAX_OPERATION
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} MV_CESA_OPERATION;
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#define MV_CESA_OPERATION_OFFSET 0
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#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET)
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/* mac algorithm */
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typedef enum
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{
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MV_CESA_MAC_NULL = 0,
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MV_CESA_MAC_MD5 = 4,
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MV_CESA_MAC_SHA1 = 5,
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MV_CESA_MAC_HMAC_MD5 = 6,
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MV_CESA_MAC_HMAC_SHA1 = 7,
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} MV_CESA_MAC_MODE;
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#define MV_CESA_MAC_MODE_OFFSET 4
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#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET)
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typedef enum
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{
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MV_CESA_MAC_DIGEST_FULL = 0,
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MV_CESA_MAC_DIGEST_96B = 1,
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} MV_CESA_MAC_DIGEST_SIZE;
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#define MV_CESA_MAC_DIGEST_SIZE_BIT 7
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#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT)
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typedef enum
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{
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MV_CESA_CRYPTO_NULL = 0,
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MV_CESA_CRYPTO_DES = 1,
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MV_CESA_CRYPTO_3DES = 2,
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MV_CESA_CRYPTO_AES = 3,
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} MV_CESA_CRYPTO_ALG;
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#define MV_CESA_CRYPTO_ALG_OFFSET 8
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#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET)
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/* direction */
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typedef enum
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{
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MV_CESA_DIR_ENCODE = 0,
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MV_CESA_DIR_DECODE = 1,
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} MV_CESA_DIRECTION;
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#define MV_CESA_DIRECTION_BIT 12
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#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT)
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/* crypto IV mode */
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typedef enum
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{
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MV_CESA_CRYPTO_ECB = 0,
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MV_CESA_CRYPTO_CBC = 1,
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/* NO HW Support */
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MV_CESA_CRYPTO_CTR = 10,
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} MV_CESA_CRYPTO_MODE;
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#define MV_CESA_CRYPTO_MODE_BIT 16
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#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT)
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/* 3DES mode */
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typedef enum
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{
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MV_CESA_CRYPTO_3DES_EEE = 0,
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MV_CESA_CRYPTO_3DES_EDE = 1,
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} MV_CESA_CRYPTO_3DES_MODE;
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#define MV_CESA_CRYPTO_3DES_MODE_BIT 20
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#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT)
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/* AES Key Length */
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typedef enum
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{
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MV_CESA_CRYPTO_AES_KEY_128 = 0,
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MV_CESA_CRYPTO_AES_KEY_192 = 1,
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MV_CESA_CRYPTO_AES_KEY_256 = 2,
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} MV_CESA_CRYPTO_AES_KEY_LEN;
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#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24
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#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET)
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/* Fragmentation mode */
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typedef enum
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{
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MV_CESA_FRAG_NONE = 0,
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MV_CESA_FRAG_FIRST = 1,
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MV_CESA_FRAG_LAST = 2,
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MV_CESA_FRAG_MIDDLE = 3,
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} MV_CESA_FRAG_MODE;
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#define MV_CESA_FRAG_MODE_OFFSET 30
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#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET)
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/*---------------------------------------------------------------------------*/
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/********** Security Accelerator Command Register **************/
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#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00)
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#define MV_CESA_CMD_CHAN_ENABLE_BIT 0
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#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT)
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#define MV_CESA_CMD_CHAN_DISABLE_BIT 2
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#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT)
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/********** Security Accelerator Descriptor Pointers Register **********/
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#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04)
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/********** Security Accelerator Configuration Register **********/
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#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08)
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#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0
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#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT)
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#define MV_CESA_CFG_WAIT_DMA_BIT 7
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#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT)
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#define MV_CESA_CFG_ACT_DMA_BIT 9
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#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT)
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#define MV_CESA_CFG_CHAIN_MODE_BIT 11
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#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT)
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/********** Security Accelerator Status Register ***********/
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#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C)
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#define MV_CESA_STATUS_ACTIVE_BIT 0
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#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT)
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#define MV_CESA_STATUS_DIGEST_ERR_BIT 8
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#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT)
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/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */
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#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20)
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/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */
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#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24)
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#define MV_CESA_CAUSE_AUTH_MASK (1 << 0)
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#define MV_CESA_CAUSE_DES_MASK (1 << 1)
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#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2)
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#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3)
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#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4)
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#define MV_CESA_CAUSE_ACC_BIT 5
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#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT)
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#define MV_CESA_CAUSE_ACC_DMA_BIT 7
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#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT)
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#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT)
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#define MV_CESA_CAUSE_DMA_COMPL_BIT 9
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#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT)
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#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10
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#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT)
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#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11
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#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT)
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#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38)
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#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20)
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#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24)
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#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2))
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#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00)
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#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04)
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#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08)
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#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c)
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#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10)
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#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18)
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#define MV_CESA_AUTH_ALGORITHM_BIT 0
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#define MV_CESA_AUTH_ALGORITHM_MD5 (0<<AUTH_ALGORITHM_BIT)
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#define MV_CESA_AUTH_ALGORITHM_SHA1 (1<<AUTH_ALGORITHM_BIT)
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#define MV_CESA_AUTH_IV_MODE_BIT 1
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#define MV_CESA_AUTH_IV_MODE_INIT (0<<AUTH_IV_MODE_BIT)
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#define MV_CESA_AUTH_IV_MODE_CONTINUE (1<<AUTH_IV_MODE_BIT)
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#define MV_CESA_AUTH_DATA_BYTE_SWAP_BIT 2
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#define MV_CESA_AUTH_DATA_BYTE_SWAP_MASK (1<<AUTH_DATA_BYTE_SWAP_BIT)
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#define MV_CESA_AUTH_IV_BYTE_SWAP_BIT 4
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#define MV_CESA_AUTH_IV_BYTE_SWAP_MASK (1<<AUTH_IV_BYTE_SWAP_BIT)
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#define MV_CESA_AUTH_TERMINATION_BIT 31
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#define MV_CESA_AUTH_TERMINATION_MASK (1<<AUTH_TERMINATION_BIT)
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/*************** TDMA Control Register ************************************************/
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#define MV_CESA_TDMA_CTRL_REG (MV_CESA_TDMA_REG_BASE + 0x840)
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#define MV_CESA_TDMA_BURST_32B 3
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#define MV_CESA_TDMA_BURST_128B 4
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#define MV_CESA_TDMA_DST_BURST_OFFSET 0
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#define MV_CESA_TDMA_DST_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_DST_BURST_OFFSET)
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#define MV_CESA_TDMA_DST_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_DST_BURST_OFFSET)
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#define MV_CESA_TDMA_OUTSTAND_READ_EN_BIT 4
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#define MV_CESA_TDMA_OUTSTAND_READ_EN_MASK (1<<MV_CESA_TDMA_OUTSTAND_READ_EN_BIT)
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#define MV_CESA_TDMA_SRC_BURST_OFFSET 6
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#define MV_CESA_TDMA_SRC_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_SRC_BURST_OFFSET)
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#define MV_CESA_TDMA_SRC_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_SRC_BURST_OFFSET)
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#define MV_CESA_TDMA_CHAIN_MODE_BIT 9
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#define MV_CESA_TDMA_NON_CHAIN_MODE_MASK (1<<MV_CESA_TDMA_CHAIN_MODE_BIT)
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#define MV_CESA_TDMA_BYTE_SWAP_BIT 11
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#define MV_CESA_TDMA_BYTE_SWAP_MASK (0 << MV_CESA_TDMA_BYTE_SWAP_BIT)
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#define MV_CESA_TDMA_NO_BYTE_SWAP_MASK (1 << MV_CESA_TDMA_BYTE_SWAP_BIT)
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#define MV_CESA_TDMA_ENABLE_BIT 12
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#define MV_CESA_TDMA_ENABLE_MASK (1<<MV_CESA_TDMA_ENABLE_BIT)
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#define MV_CESA_TDMA_FETCH_NEXT_DESC_BIT 13
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#define MV_CESA_TDMA_FETCH_NEXT_DESC_MASK (1<<MV_CESA_TDMA_FETCH_NEXT_DESC_BIT)
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#define MV_CESA_TDMA_CHAN_ACTIVE_BIT 14
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#define MV_CESA_TDMA_CHAN_ACTIVE_MASK (1<<MV_CESA_TDMA_CHAN_ACTIVE_BIT)
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/*------------------------------------------------------------------------------------*/
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#define MV_CESA_TDMA_BYTE_COUNT_REG (MV_CESA_TDMA_REG_BASE + 0x800)
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#define MV_CESA_TDMA_SRC_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x810)
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#define MV_CESA_TDMA_DST_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x820)
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#define MV_CESA_TDMA_NEXT_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x830)
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#define MV_CESA_TDMA_CURR_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x870)
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#define MV_CESA_TDMA_ERROR_CAUSE_REG (MV_CESA_TDMA_REG_BASE + 0x8C0)
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#define MV_CESA_TDMA_ERROR_MASK_REG (MV_CESA_TDMA_REG_BASE + 0x8C4)
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#endif /* __mvCesaRegs_h__ */
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