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2aba2b32ce
Runtime-tested on: - Linksprite pcDuino v2 (A10) - Olimex Olinuxino Micro (A20) - Bananapi M2 Berry (V40) - Bananapi P2 Zero (H2+) - OrangePi Zero2 (H616) Patches refreshed where required. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
33 lines
1003 B
Diff
33 lines
1003 B
Diff
From a58eb20fb80f478038243e9e0f30f6984725e265 Mon Sep 17 00:00:00 2001
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From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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Date: Tue, 6 Jan 2015 15:47:18 +0100
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Subject: sun6i: Sync PLL1 multipliers/dividers with Boot1
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This change syncs up the multipliers and dividers used to initialize
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PLL1 (i.e. the fast clock driving the ARM cores) with the values used
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in Allwinner's Boot1 on sun6i.
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More specifically, the following settings are now used:
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* up to 768MHz: mul=2, div=2 (was: mul=1, div=1)
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* up to 1152MHz: mul=3, div=2 (unchanged)
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* above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
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--- a/arch/arm/mach-sunxi/clock_sun6i.c
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+++ b/arch/arm/mach-sunxi/clock_sun6i.c
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@@ -128,11 +128,12 @@ void clock_set_pll1(unsigned int clk)
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int p = 0;
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- int k = 1;
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- int m = 1;
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+ int k = 2;
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+ int m = 2;
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if (clk > 1152000000) {
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- k = 2;
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+ k = 4;
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+ m = 2;
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} else if (clk > 768000000) {
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k = 4;
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m = 2;
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