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eb974c3b3e
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/18683 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
57 lines
1.2 KiB
Diff
57 lines
1.2 KiB
Diff
From af7ec140ddc1815bc462109792d95bcad05cfbc4 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Tue, 9 Apr 2024 00:50:36 +0200
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Subject: [PATCH] arm64: dts: rockchip: add upper USB3 port to rock-5a
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Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from
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Radxa Rock 5 Model A. The lower one is already supported.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240408225109.128953-10-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3588s-rock-5a.dts | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
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@@ -698,6 +698,14 @@
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};
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};
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+&u2phy0 {
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+ status = "okay";
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+};
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+
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+&u2phy0_otg {
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+ status = "okay";
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+};
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+
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&u2phy2 {
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status = "okay";
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};
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@@ -721,6 +729,11 @@
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status = "okay";
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};
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+&usbdp_phy0 {
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+ status = "okay";
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+ rockchip,dp-lane-mux = <2 3>;
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+};
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+
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&usb_host0_ehci {
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status = "okay";
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pinctrl-names = "default";
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@@ -731,6 +744,11 @@
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status = "okay";
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};
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+&usb_host0_xhci {
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+ dr_mode = "host";
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+ status = "okay";
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+};
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+
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&usb_host1_ehci {
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status = "okay";
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};
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