openwrt/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts
Christian Marangi 4589fa38c5
mpc85xx: convert to new LED color/function format where possible
Initial conversion to new LED color/function format
and drop label format where possible. The same label
is composed at runtime.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-02-07 14:48:40 +01:00

369 lines
6.9 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later or MIT
/include/ "fsl/p1020si-pre.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Extreme Networks WS-AP3825i";
compatible = "extreme-networks,ws-ap3825i";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet2;
led-boot = &led_power_green;
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_red;
};
chosen {
bootargs-override = "console=ttyS0,115200";
stdout-path = &serial0;
};
memory {
device_type = "memory";
};
leds {
compatible = "gpio-leds";
wifi1 {
gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
label = "green:radio1";
linux,default-trigger = "phy0tpt";
};
wifi2 {
gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
label = "green:radio2";
linux,default-trigger = "phy1tpt";
};
led_power_green: power_green {
gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
};
led_power_red: power_red {
gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
};
lan1_red {
gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
label = "red:lan1";
};
lan1_green {
gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
label = "green:lan1";
};
lan2_red {
gpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;
label = "red:lan2";
};
lan2_green {
gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
label = "green:lan2";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
nor@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
device-width = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
compatible = "denx,fit";
reg = <0x0 0x3d60000>;
label = "firmware";
};
partition@3d60000 {
reg = <0x3d60000 0x20000>;
label = "calib";
read-only;
};
partition@3d80000{
reg = <0x3d80000 0x80000>;
label = "u-boot";
read-only;
};
partition@3e00000{
reg = <0x3e00000 0x100000>;
label = "nvram";
read-only;
};
partition@3f00000 {
reg = <0x3f00000 0x20000>;
label = "cfg2";
};
partition@3f20000 {
reg = <0x3f20000 0x20000>;
label = "cfg1";
};
};
};
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
gpio0: gpio-controller@fc00 {
};
mdio@24000 {
phy0: ethernet-phy@0 {
/* interrupts = <3 1 0 0>; */
reg = <0x5>;
reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
};
phy2: ethernet-phy@2 {
/* interrupts = <1 1 0 0>; */
reg = <0x6>;
reset-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
};
};
mdio@25000 {
status = "disabled";
};
mdio@26000 {
status = "disabled";
};
enet0: ethernet@b0000 {
status = "okay";
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
status = "disabled";
};
enet2: ethernet@b2000 {
status = "okay";
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
usb@22000 {
phy_type = "ulpi";
dr_mode = "host";
};
usb@23000 {
status = "disabled";
};
};
pci0: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0 0xffe09000 0 0x1000>;
/* Filled by U-Boot */
bus-range = <0x00 0x01>;
dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
0x00 0x100000 0x42000000 0x00 0x00 0x00
0x00 0x00 0x10000000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
/* Filled by U-Boot */
bus-range = <0x00 0x01>;
dma-ranges = <0x2000000 0x00 0xfff00000 0x00
0xffe00000 0x00 0x100000 0x42000000
0x00 0x00 0x00 0x00 0x00 0x10000000>;
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
&soc {
led_spi {
/*
* This is currently non-functioning because the spi-gpio
* driver refuses to register when presented with this node.
*/
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
spi_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <100000>;
};
};
};
/include/ "fsl/p1020si-post.dtsi"
/ {
cpus {
PowerPC,P1020@0 {
bus-frequency = <399999996>;
timebase-frequency = <50000000>;
clock-frequency = <799999992>;
d-cache-block-size = <0x20>;
d-cache-size = <0x8000>;
d-cache-sets = <0x80>;
i-cache-block-size = <0x20>;
i-cache-size = <0x8000>;
i-cache-sets = <0x80>;
cpu-release-addr = <0x0 0x0ffff280>;
status = "okay";
enable-method = "spin-table";
};
PowerPC,P1020@1 {
bus-frequency = <399999996>;
timebase-frequency = <50000000>;
clock-frequency = <799999992>;
d-cache-block-size = <0x20>;
d-cache-size = <0x8000>;
d-cache-sets = <0x80>;
i-cache-block-size = <0x20>;
i-cache-size = <0x8000>;
i-cache-sets = <0x80>;
cpu-release-addr = <0x0 0x0ffff2a0>;
status = "disabled";
enable-method = "spin-table";
};
};
memory {
reg = <0x0 0x0 0x0 0x10000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpu1-bootpage@ff00000 {
/* Reserve upper 1 MB for second-core-bootpage */
reg = <0x0 0xff00000 0x0 0x100000>;
};
};
soc@ffe00000 {
bus-frequency = <399999996>;
serial@4600 {
clock-frequency = <399999996>;
};
serial@4500 {
clock-frequency = <399999996>;
};
pic@40000 {
clock-frequency = <399999996>;
};
};
localbus@ffe05000 {
bus-frequency = <24999999>;
};
};
&enet0 {
rx-stash-idx = <0x00>;
rx-stash-len = <0x60>;
bd-stash;
};
&enet2 {
rx-stash-idx = <0x00>;
rx-stash-len = <0x60>;
bd-stash;
};
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
* change the sysfs path of our wireless netdevs.
*/
/ {
aliases {
/delete-property/ pci0;
/delete-property/ pci1;
};
};