102009f3ea
with 6.1, the kernel no longer fitted into the 16 MiB and kicking down the can and increasing KERNEL_SIZE to 20 MiB didn't help as the device failed to boot. Using 'kernel-bin | gzip | uimage gzip' didn't work since the uboot does not have enough heap to decompress these big kernels. And finally playing around with uboot was more a hassle than converting this device to take the simpleImage-boot-route in the future. Note: The device now takes even longer on the first boot-up after the flash due to JFFS2 initializing all the remaining flash. Be prepared to wait up to 10 minutes before the green status LED stops blinking and will shine a solid green! (On the plus site: the device now has ~10 MiB of additional space for rootfs+rootfs_data). Note2: This patch includes a kernel patch refresh. Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
425 lines
9.3 KiB
Plaintext
425 lines
9.3 KiB
Plaintext
/*
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* Aerohive HiveAP-330 Device Tree Source
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*
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* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/include/ "fsl/p1020si-pre.dtsi"
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/ {
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model = "Aerohive HiveAP-330";
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compatible = "aerohive,hiveap-330";
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aliases {
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led-boot = &led_power_green;
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led-failsafe = &led_fault_red;
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led-running = &led_power_green;
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led-upgrade = &led_fault_red;
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label-mac-device = &enet0;
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spi0 = &spi0;
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};
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chosen {
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/*
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* not yet implemented.
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* stdout-path = &serial0 ":9600n8";
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* <https://www.spinics.net/lists/devicetree-compiler/msg02487.html>
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*
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* this should work... but it doesn't because CONFIG_CMDLINE in our
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* OpenWrt's target config sets "console=ttyS0,115200"
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* stdout-path = "/soc@ffe00000/serial@4500:9600n8";
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*/
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bootargs = "console=ttyS0,9600n8";
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};
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cpus {
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PowerPC,P1020@0 {
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i-cache-sets = <0x80>;
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i-cache-size = <0x8000>;
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i-cache-block-size = <0x20>;
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d-cache-sets = <0x80>;
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d-cache-size = <0x8000>;
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d-cache-block-size = <0x20>;
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status = "okay";
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clock-frequency = <533333328>; /* 533.33 MHz */
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bus-frequency = <266666664>; /* 266.66 MHz */
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timebase-frequency = <33333333>; /* 33.33 MHz */
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};
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PowerPC,P1020@1 {
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i-cache-sets = <0x80>;
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i-cache-size = <0x8000>;
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i-cache-block-size = <0x20>;
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d-cache-sets = <0x80>;
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d-cache-size = <0x8000>;
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d-cache-block-size = <0x20>;
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cpu-release-addr = <0x00 0xffff240>;
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enable-method = "spin-table";
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status = "disabled";
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clock-frequency = <533333328>;
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bus-frequency = <266666664>;
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timebase-frequency = <33333333>;
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};
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};
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memory {
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x00 0x00 0x00 0x10000000>;
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device_type = "memory";
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};
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/*
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* Usually, u-boot provided /memreserve/ properties by adding them during boot.
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* these have been converted to reserved-memory entries.
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*/
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/*
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* /memreserve/ 0x0000000000ffa000 0x0000000000004000;
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* The kernel complains when booting:
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*
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* | OF: fdt: Reserved memory: failed to reserve memory for node
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* 'firmware@ffa000': base 0x00ffa000, size 0 MiB
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*
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* But this likely uboot's bootargs + modified DTB. And if so, we don't care.
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* This is because we rely on our own dtb that's in the simpleImage.
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*
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* Note: This is backed up by u-boot. just before the kernel executes
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* it prints this final line:
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* | Loading Device Tree to 00ff9000, end 00fff1c4 ... OK
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*
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* firmware@ffa000 {
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* reg = <0x0 0xffa000 0x0 0x4000>;
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* no-map;
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* };
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*/
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// /memreserve/ 0x000000000fe2f000 0x0000000000000021;
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firmware@fe2f000 {
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reg = <0x0 0xfe2f000 0x0 0x21>;
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no-map;
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};
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/*
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* /memreserve/ 0x000000000ffff000 0x0000000000001000;
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* that's the spin-table - see second CPU core binding.
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*/
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firmware@ffff000 {
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reg = <0x0 0xffff000 0x0 0x1000>;
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no-map;
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};
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};
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board_lbc: lbc: localbus@ffe05000 {
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bus-frequency = <16666666>; /* 16.66 MHz */
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
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nor@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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firmware@0 {
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reg = <0x0 0x3f00000>;
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label = "firmware";
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/*
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* This unknown/invalid compatible prevents
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* openwrt's mtdsplit_fit to go off a tangent if it
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* finds a magic value inside the uncompressed kernel
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* at a blocksized aligned place.
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*/
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compatible = "areohive,hiveap-330-image";
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};
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partition@0 {
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reg = <0x0 0x40000>;
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label = "dtb";
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};
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partition@40000 {
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compatible = "openwrt,uimage", "denx,uimage";
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reg = <0x40000 0x3ec0000>;
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label = "kernel";
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};
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partition@3f00000 {
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reg = <0x3f00000 0x20000>;
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label = "hw-info";
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_hwinfo_0: macaddr@0 {
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compatible = "mac-base";
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reg = <0x0 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@3f20000 {
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reg = <0x3f20000 0x20000>;
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label = "boot-info";
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read-only;
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};
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partition@3f40000 {
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reg = <0x3f40000 0x20000>;
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label = "boot-info-backup";
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read-only;
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};
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partition@3f60000 {
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reg = <0x3f60000 0x20000>;
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label = "u-boot-env";
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};
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partition@3f80000 {
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reg = <0x3f80000 0x80000>;
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label = "u-boot";
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read-only;
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};
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};
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};
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};
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board_soc: soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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bus-frequency = <266666664>;
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spi0: spi@7000 {
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#address-cells = <1>;
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#size-cells = <0>;
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temperature-sensor@1 {
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compatible = "ti,tmp125";
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reg = <1>;
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spi-max-frequency = <5000000>;
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};
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};
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i2c@3100 {
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tpm@29 {
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compatible = "atmel,at97sc3204t";
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reg = <0x29>;
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};
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lp5521@32 {
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compatible = "national,lp5521";
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reg = <0x32>;
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clock-mode = /bits/ 8 <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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#if 1
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led_fault_red: led@0 {
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reg = <0>;
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chan-name = "fault:red";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_FAULT;
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};
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led_power_green: led@1 {
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reg = <1>;
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chan-name = "power:green";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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};
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led@2{
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reg = <2>;
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chan-name = "blue";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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color = <LED_COLOR_ID_BLUE>;
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};
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#else
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/*
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* openwrt isn't ready to handle multi-intensity leds yet
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* # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity
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* # echo 255 > /sys/class/leds/tricolor/brightness
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*/
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rgbled-0 {
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_RGB>;
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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chan-name = "tricolor";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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color = <LED_COLOR_ID_RED>;
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};
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led@1 {
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reg = <1>;
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chan-name = "tricolor";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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color = <LED_COLOR_ID_GREEN>;
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};
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led@2{
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reg = <2>;
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chan-name = "tricolor";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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color = <LED_COLOR_ID_BLUE>;
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};
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};
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#endif
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};
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eeprom@51 {
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/*
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* 1Kbit I2C/SMBus EEPROM with SHA-1 Engine
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* Aerohive calls it "dallas".
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*/
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compatible = "adi,ds28cn01";
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reg = <0x51>;
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read-only;
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};
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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/* interrupts = <3 1 0 0>; */
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reg = <0x1>;
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};
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phy1: ethernet-phy@1 {
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/* interrupts = <2 1 0 0>; */
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reg = <0x2>;
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};
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};
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mdio@25000 {
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status = "disabled";
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};
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mdio@26000 {
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status = "disabled";
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};
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enet0: ethernet@b0000 {
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rx-stash-idx = <0x00>;
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rx-stash-len = <0x60>;
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bd-stash;
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status = "okay";
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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nvmem-cells = <&macaddr_hwinfo_0 0>;
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nvmem-cell-names = "mac-address";
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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rx-stash-idx = <0x00>;
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rx-stash-len = <0x60>;
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bd-stash;
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status = "okay";
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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nvmem-cells = <&macaddr_hwinfo_0 1>;
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nvmem-cell-names = "mac-address";
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};
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gpio0: gpio-controller@fc00 {
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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usb@23000 {
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status = "disabled";
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};
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};
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pci0: pcie@ffe09000 {
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reg = <0x0 0xffe09000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>,
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<0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x20000000>,
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<0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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reg = <0x0 0xffe0a000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,
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<0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000 0x2000000 0x0 0xc0000000 0x0 0x20000000>,
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<0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
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};
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};
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buttons {
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compatible = "gpio-keys";
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reset {
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label = "Reset button";
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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/include/ "fsl/p1020si-post.dtsi"
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&serial0 {
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clock-frequency = <266666664>;
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};
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&serial1 {
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clock-frequency = <266666664>;
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};
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/*
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* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
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* aliases to determine PCI domain numbers, drop aliases so as not to
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* change the sysfs path of our wireless netdevs.
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*/
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/ {
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aliases {
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/delete-property/ pci0;
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/delete-property/ pci1;
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};
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};
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