fe9d2ccbc3
Move accepted patches to backport folder, re-add previously removed patch
which caused havoc on MT7621 and add the (still pending) fix.
Fixes: d40691a5fb ("generic: 6.1, 6.6: mt7530: import pending patches")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
186 lines
5.5 KiB
Diff
186 lines
5.5 KiB
Diff
From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Mon, 22 Apr 2024 10:15:10 +0300
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Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for
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MT7530 switch
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The p5_intf_sel pointer is used to store the information of whether PHY
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muxing is used or not. PHY muxing is a feature specific to port 5 of the
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MT7530 switch. Do not use it for other switch models.
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Rename the pointer to p5_mode to store the mode the port is being used in.
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Rename the p5_interface_select enum to mt7530_p5_mode, the string
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representation to mt7530_p5_mode_str, and the enum elements.
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If PHY muxing is not detected, the default mode, GMAC5, will be used.
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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---
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drivers/net/dsa/mt7530.c | 62 +++++++++++++++++-----------------------
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drivers/net/dsa/mt7530.h | 15 +++++-----
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2 files changed, 33 insertions(+), 44 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -857,19 +857,15 @@ mt7530_set_ageing_time(struct dsa_switch
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return 0;
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}
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-static const char *p5_intf_modes(unsigned int p5_interface)
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+static const char *mt7530_p5_mode_str(unsigned int mode)
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{
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- switch (p5_interface) {
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- case P5_DISABLED:
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- return "DISABLED";
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- case P5_INTF_SEL_PHY_P0:
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- return "PHY P0";
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- case P5_INTF_SEL_PHY_P4:
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- return "PHY P4";
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- case P5_INTF_SEL_GMAC5:
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- return "GMAC5";
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+ switch (mode) {
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+ case MUX_PHY_P0:
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+ return "MUX PHY P0";
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+ case MUX_PHY_P4:
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+ return "MUX PHY P4";
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default:
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- return "unknown";
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+ return "GMAC5";
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}
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}
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@@ -886,23 +882,23 @@ static void mt7530_setup_port5(struct ds
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val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
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val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
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- switch (priv->p5_intf_sel) {
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- case P5_INTF_SEL_PHY_P0:
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- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
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+ switch (priv->p5_mode) {
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+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
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+ case MUX_PHY_P0:
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val |= MHWTRAP_PHY0_SEL;
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fallthrough;
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- case P5_INTF_SEL_PHY_P4:
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- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
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+
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+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
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+ case MUX_PHY_P4:
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val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
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/* Setup the MAC by default for the cpu port */
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mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
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break;
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- case P5_INTF_SEL_GMAC5:
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- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
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- val &= ~MHWTRAP_P5_DIS;
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- break;
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+
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+ /* GMAC5: P5 -> SoC MAC or external PHY */
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default:
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+ val &= ~MHWTRAP_P5_DIS;
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break;
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}
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@@ -930,8 +926,8 @@ static void mt7530_setup_port5(struct ds
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mt7530_write(priv, MT7530_MHWTRAP, val);
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- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
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- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
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+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
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+ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
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mutex_unlock(&priv->reg_mutex);
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}
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@@ -2476,13 +2472,11 @@ mt7530_setup(struct dsa_switch *ds)
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if (ret)
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return ret;
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- /* Setup port 5 */
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- if (!dsa_is_unused_port(ds, 5)) {
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- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
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- } else {
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+ /* Check for PHY muxing on port 5 */
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+ if (dsa_is_unused_port(ds, 5)) {
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/* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
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- * Set priv->p5_intf_sel to the appropriate value if PHY muxing
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- * is detected.
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+ * Set priv->p5_mode to the appropriate value if PHY muxing is
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+ * detected.
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*/
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for_each_child_of_node(dn, mac_np) {
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if (!of_device_is_compatible(mac_np,
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@@ -2506,17 +2500,16 @@ mt7530_setup(struct dsa_switch *ds)
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}
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id = of_mdio_parse_addr(ds->dev, phy_node);
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if (id == 0)
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- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
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+ priv->p5_mode = MUX_PHY_P0;
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if (id == 4)
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- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
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+ priv->p5_mode = MUX_PHY_P4;
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}
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of_node_put(mac_np);
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of_node_put(phy_node);
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break;
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}
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- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
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- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
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+ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
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mt7530_setup_port5(ds, interface);
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}
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@@ -2654,9 +2647,6 @@ mt7531_setup(struct dsa_switch *ds)
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MT7531_EXT_P_MDIO_12);
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}
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- if (!dsa_is_unused_port(ds, 5))
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- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
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-
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mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
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MT7531_GPIO0_INTERRUPT);
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -708,12 +708,11 @@ struct mt7530_port {
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struct phylink_pcs *sgmii_pcs;
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};
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-/* Port 5 interface select definitions */
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-enum p5_interface_select {
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- P5_DISABLED,
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- P5_INTF_SEL_PHY_P0,
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- P5_INTF_SEL_PHY_P4,
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- P5_INTF_SEL_GMAC5,
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+/* Port 5 mode definitions of the MT7530 switch */
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+enum mt7530_p5_mode {
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+ GMAC5,
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+ MUX_PHY_P0,
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+ MUX_PHY_P4,
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};
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struct mt7530_priv;
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@@ -776,7 +775,7 @@ struct mt753x_info {
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* @ports: Holding the state among ports
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* @reg_mutex: The lock for protecting among process accessing
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* registers
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- * @p5_intf_sel: Holding the current port 5 interface select
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+ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
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* @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
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* has got SGMII
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* @irq: IRQ number of the switch
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@@ -798,7 +797,7 @@ struct mt7530_priv {
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const struct mt753x_info *info;
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unsigned int id;
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bool mcm;
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- enum p5_interface_select p5_intf_sel;
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+ enum mt7530_p5_mode p5_mode;
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bool p5_sgmii;
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u8 mirror_rx;
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u8 mirror_tx;
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