4354b34f6f
Backport lots upstream changes, many of them fixes, for the mt7530 DSA driver, similar to how it was done for Linux 6.1 in the previous commit. The remaining differences compared to the upstream driver are only the 'slave' -> 'user', 'master' -> 'conduit' language change in DSA and the rename of 'struct ethtool_eee' to 'struct ethtool_keee' as well as tree-wide replacement of ethtool_sprintf with ethtool_puts, all of them do not have any functional impact. Apart from some minor bug fixes and style improvements the switch should now behave more conformant when it comes to link-local frames, and we will again be able to cleanly pick patches from upstream. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
147 lines
5.1 KiB
Diff
147 lines
5.1 KiB
Diff
From c33899a6a8c1a5723afbfc075600aba2e2bdbea7 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Tue, 6 Feb 2024 01:08:04 +0300
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Subject: [PATCH 14/30] net: dsa: mt7530: simplify mt7530_pad_clk_setup()
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This code is from before this driver was converted to phylink API. Phylink
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deals with the unsupported interface cases before mt7530_pad_clk_setup() is
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run. Therefore, the default case would never run. However, it must be
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defined nonetheless to handle all the remaining enumeration values, the
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phy-modes.
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Switch to if statement for RGMII and return which simplifies the code and
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saves an indent.
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Set P6_INTF_MODE, which is the three least significant bits of the
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MT7530_P6ECR register, to 0 for RGMII even though it will already be 0
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after reset. This is to keep supporting dynamic reconfiguration of the port
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in the case the interface changes from TRGMII to RGMII.
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Disable the TRGMII clocks for all cases. They will be enabled if TRGMII is
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being used.
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Read XTAL after checking for RGMII as it's only needed for the TRGMII
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interface mode.
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Reviewed-by: Daniel Golle <daniel@makrotopia.org>
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Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
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Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-3-d7d92a185cb1@arinc9.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/mt7530.c | 91 ++++++++++++++++++----------------------
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1 file changed, 40 insertions(+), 51 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -418,65 +418,54 @@ static int
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mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
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{
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struct mt7530_priv *priv = ds->priv;
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- u32 ncpo1, ssc_delta, trgint, xtal;
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+ u32 ncpo1, ssc_delta, xtal;
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- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
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+ /* Disable the MT7530 TRGMII clocks */
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+ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
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- switch (interface) {
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- case PHY_INTERFACE_MODE_RGMII:
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- trgint = 0;
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- break;
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- case PHY_INTERFACE_MODE_TRGMII:
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- trgint = 1;
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- if (xtal == HWTRAP_XTAL_25MHZ)
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- ssc_delta = 0x57;
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- else
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- ssc_delta = 0x87;
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- if (priv->id == ID_MT7621) {
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- /* PLL frequency: 125MHz: 1.0GBit */
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- if (xtal == HWTRAP_XTAL_40MHZ)
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- ncpo1 = 0x0640;
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- if (xtal == HWTRAP_XTAL_25MHZ)
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- ncpo1 = 0x0a00;
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- } else { /* PLL frequency: 250MHz: 2.0Gbit */
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- if (xtal == HWTRAP_XTAL_40MHZ)
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- ncpo1 = 0x0c80;
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- if (xtal == HWTRAP_XTAL_25MHZ)
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- ncpo1 = 0x1400;
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- }
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- break;
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- default:
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- dev_err(priv->dev, "xMII interface %d not supported\n",
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- interface);
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- return -EINVAL;
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+ if (interface == PHY_INTERFACE_MODE_RGMII) {
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+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
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+ P6_INTF_MODE(0));
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+ return 0;
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}
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- mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
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- P6_INTF_MODE(trgint));
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+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
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- if (trgint) {
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- /* Disable the MT7530 TRGMII clocks */
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- core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
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-
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- /* Setup the MT7530 TRGMII Tx Clock */
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- core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
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- core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
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- core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
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- core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
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- core_write(priv, CORE_PLL_GROUP4,
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- RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
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- RG_SYSPLL_BIAS_LPF_EN);
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- core_write(priv, CORE_PLL_GROUP2,
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- RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
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- RG_SYSPLL_POSDIV(1));
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- core_write(priv, CORE_PLL_GROUP7,
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- RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
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- RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
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+ xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
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- /* Enable the MT7530 TRGMII clocks */
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- core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
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+ if (xtal == HWTRAP_XTAL_25MHZ)
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+ ssc_delta = 0x57;
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+ else
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+ ssc_delta = 0x87;
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+
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+ if (priv->id == ID_MT7621) {
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+ /* PLL frequency: 125MHz: 1.0GBit */
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+ if (xtal == HWTRAP_XTAL_40MHZ)
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+ ncpo1 = 0x0640;
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+ if (xtal == HWTRAP_XTAL_25MHZ)
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+ ncpo1 = 0x0a00;
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+ } else { /* PLL frequency: 250MHz: 2.0Gbit */
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+ if (xtal == HWTRAP_XTAL_40MHZ)
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+ ncpo1 = 0x0c80;
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+ if (xtal == HWTRAP_XTAL_25MHZ)
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+ ncpo1 = 0x1400;
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}
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+ /* Setup the MT7530 TRGMII Tx Clock */
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+ core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
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+ core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
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+ core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
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+ core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
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+ core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
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+ RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
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+ core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL |
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+ RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1));
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+ core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG |
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+ RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
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+
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+ /* Enable the MT7530 TRGMII clocks */
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+ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
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+
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return 0;
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}
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