bb907d8d44
PMD Global Transmit Disable bit should be cleared for normal operation. This should be HW default, however I found that on Asus RT-AX89X that uses AQR113C PHY and firmware 5.4 this bit is set by default. With this bit set the AQR cannot achieve a link with its link-partner and it took me multiple hours of digging through the vendor GPL source to find this out, so lets always clear this bit during .config_init() to avoid a situation like this in the future. aqr107_wait_processor_intensive_op() is moved up because datasheet notes that any changes to this bit are processor intensive. This is a modified version of patch that got merged upstream as AQR113C has a separate config_init() upstream. Link: https://github.com/openwrt/openwrt/pull/15840 Signed-off-by: Robert Marko <robimarko@gmail.com>
104 lines
3.3 KiB
Diff
104 lines
3.3 KiB
Diff
From cffac22c9215f1883d3848c788f9b03656dced27 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 11 Feb 2024 18:39:19 +0100
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Subject: [PATCH] net: phy: aquantia: clear PMD Global Transmit Disable bit
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during init
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PMD Global Transmit Disable bit should be cleared for normal operation.
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This should be HW default, however I found that on Asus RT-AX89X that uses
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AQR113C PHY and firmware 5.4 this bit is set by default.
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With this bit set the AQR cannot achieve a link with its link-partner and
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it took me multiple hours of digging through the vendor GPL source to find
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this out, so lets always clear this bit during .config_init() to avoid a
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situation like this in the future.
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aqr107_wait_processor_intensive_op() is moved up because datasheet notes
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that any changes to this bit are processor intensive.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/net/phy/aquantia/aquantia_main.c | 57 ++++++++++++++----------
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1 file changed, 33 insertions(+), 24 deletions(-)
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--- a/drivers/net/phy/aquantia/aquantia_main.c
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+++ b/drivers/net/phy/aquantia/aquantia_main.c
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@@ -507,6 +507,30 @@ static void aqr107_chip_info(struct phy_
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fw_major, fw_minor, build_id, prov_id);
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}
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+static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
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+{
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+ int val, err;
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+
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+ /* The datasheet notes to wait at least 1ms after issuing a
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+ * processor intensive operation before checking.
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+ * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
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+ * because that just determines the maximum time slept, not the minimum.
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+ */
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+ usleep_range(1000, 5000);
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+
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+ err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
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+ VEND1_GLOBAL_GEN_STAT2, val,
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+ !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
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+ AQR107_OP_IN_PROG_SLEEP,
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+ AQR107_OP_IN_PROG_TIMEOUT, false);
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+ if (err) {
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+ phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
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+ return err;
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+ }
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+
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+ return 0;
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+}
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+
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static int aqr107_config_init(struct phy_device *phydev)
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{
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int ret;
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@@ -530,6 +554,15 @@ static int aqr107_config_init(struct phy
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if (!ret)
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aqr107_chip_info(phydev);
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+ ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
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+ MDIO_PMD_TXDIS_GLOBAL);
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+ if (ret)
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+ return ret;
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+
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+ ret = aqr107_wait_processor_intensive_op(phydev);
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+ if (ret)
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+ return ret;
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+
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return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
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}
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@@ -600,30 +633,6 @@ static void aqr107_link_change_notify(st
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phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
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}
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-static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
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-{
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- int val, err;
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-
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- /* The datasheet notes to wait at least 1ms after issuing a
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- * processor intensive operation before checking.
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- * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
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- * because that just determines the maximum time slept, not the minimum.
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- */
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- usleep_range(1000, 5000);
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-
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- err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
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- VEND1_GLOBAL_GEN_STAT2, val,
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- !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
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- AQR107_OP_IN_PROG_SLEEP,
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- AQR107_OP_IN_PROG_TIMEOUT, false);
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- if (err) {
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- phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
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- return err;
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- }
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-
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- return 0;
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-}
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-
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static int aqr107_get_rate_matching(struct phy_device *phydev,
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phy_interface_t iface)
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{
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