2ad898e091
Removed upstreamed: generic/backport-6.1/789-STABLE-01-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch [1] generic/backport-6.1/789-STABLE-02-net-dsa-mt7530-fix-link-local-frames-that-ingress-vl.patch [2] generic/backport-6.1/789-STABLE-03-net-dsa-mt7530-fix-handling-of-all-link-local-frames.patch [3] generic/pending-6.1/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch [4] generic/pending-6.1/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch [5] Manual adjusted the following patches: mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=be4512b9ac6fc53e1ca8daccbda84f643215c547 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=f1fa919ea59655f73cb3972264e157b8831ba546 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=86c0c154a759f2af9612a04bdf29110f02dce956 4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=6b62bad2da1b338f452a9380639fc9b093d75a25 5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=f78807362828ad01db2a9ed005bf79501b620f27 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
136 lines
4.3 KiB
Diff
136 lines
4.3 KiB
Diff
From 199e7d5a7f03dd377f3a7a458360dbedd71d50ba Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Thu, 27 Jul 2023 09:07:28 +0200
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Subject: [PATCH 107/250] net: ethernet: mtk_eth_soc: enable nft hw
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flowtable_offload for MT7988 SoC
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Enable hw Packet Process Engine (PPE) for MT7988 SoC.
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Tested-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/5e86341b0220a49620dadc02d77970de5ded9efc.1690441576.git.lorenzo@kernel.org
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +++
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drivers/net/ethernet/mediatek/mtk_ppe.c | 19 +++++++++++++++----
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drivers/net/ethernet/mediatek/mtk_ppe.h | 19 ++++++++++++++++++-
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3 files changed, 36 insertions(+), 5 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -5027,6 +5027,9 @@ static const struct mtk_soc_data mt7988_
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.required_clks = MT7988_CLKS_BITMAP,
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.required_pctl = false,
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.version = 3,
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+ .offload_version = 2,
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+ .hash_offset = 4,
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+ .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma_v2),
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.rxd_size = sizeof(struct mtk_rx_dma_v2),
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--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
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+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
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@@ -422,13 +422,22 @@ int mtk_foe_entry_set_wdma(struct mtk_et
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struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
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u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
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- if (mtk_is_netsys_v2_or_greater(eth)) {
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+ switch (eth->soc->version) {
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+ case 3:
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+ *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
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+ *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
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+ MTK_FOE_IB2_WDMA_WINFO_V2;
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+ l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) |
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+ FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss);
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+ break;
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+ case 2:
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*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
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*ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
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MTK_FOE_IB2_WDMA_WINFO_V2;
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l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
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FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
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- } else {
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+ break;
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+ default:
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*ib2 &= ~MTK_FOE_IB2_PORT_MG;
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*ib2 |= MTK_FOE_IB2_WDMA_WINFO;
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if (wdma_idx)
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@@ -436,6 +445,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
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l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |
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FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |
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FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);
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+ break;
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}
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return 0;
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@@ -950,8 +960,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
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mtk_ppe_init_foe_table(ppe);
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ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
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- val = MTK_PPE_TB_CFG_ENTRY_80B |
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- MTK_PPE_TB_CFG_AGE_NON_L4 |
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+ val = MTK_PPE_TB_CFG_AGE_NON_L4 |
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MTK_PPE_TB_CFG_AGE_UNBIND |
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MTK_PPE_TB_CFG_AGE_TCP |
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MTK_PPE_TB_CFG_AGE_UDP |
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@@ -967,6 +976,8 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
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MTK_PPE_ENTRIES_SHIFT);
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if (mtk_is_netsys_v2_or_greater(ppe->eth))
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val |= MTK_PPE_TB_CFG_INFO_SEL;
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+ if (!mtk_is_netsys_v3_or_greater(ppe->eth))
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+ val |= MTK_PPE_TB_CFG_ENTRY_80B;
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ppe_w32(ppe, MTK_PPE_TB_CFG, val);
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ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
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--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
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+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
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@@ -85,6 +85,17 @@ enum {
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#define MTK_FOE_WINFO_BSS GENMASK(5, 0)
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#define MTK_FOE_WINFO_WCID GENMASK(15, 6)
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+#define MTK_FOE_WINFO_BSS_V3 GENMASK(23, 16)
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+#define MTK_FOE_WINFO_WCID_V3 GENMASK(15, 0)
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+
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+#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0)
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+#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16)
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+#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20)
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+#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21)
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+#define MTK_FOE_WINFO_PAO_IS_SP BIT(22)
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+#define MTK_FOE_WINFO_PAO_HF BIT(23)
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+#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24)
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+
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enum {
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MTK_FOE_STATE_INVALID,
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MTK_FOE_STATE_UNBIND,
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@@ -106,8 +117,13 @@ struct mtk_foe_mac_info {
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u16 pppoe_id;
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u16 src_mac_lo;
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+ /* netsys_v2 */
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u16 minfo;
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u16 winfo;
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+
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+ /* netsys_v3 */
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+ u32 w3info;
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+ u32 wpao;
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};
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/* software-only entry type */
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@@ -218,6 +234,7 @@ struct mtk_foe_ipv6_6rd {
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#define MTK_FOE_ENTRY_V1_SIZE 80
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#define MTK_FOE_ENTRY_V2_SIZE 96
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+#define MTK_FOE_ENTRY_V3_SIZE 128
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struct mtk_foe_entry {
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u32 ib1;
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@@ -228,7 +245,7 @@ struct mtk_foe_entry {
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struct mtk_foe_ipv4_dslite dslite;
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struct mtk_foe_ipv6 ipv6;
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struct mtk_foe_ipv6_6rd ipv6_6rd;
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- u32 data[23];
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+ u32 data[31];
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};
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};
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