64afcbad3d
It will be used on NanoPi R2C and OrangePi R1 Plus LTS board. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
101 lines
3.1 KiB
Diff
101 lines
3.1 KiB
Diff
From 36152f87dda4af221b16258751451d9cd3d0fb0b Mon Sep 17 00:00:00 2001
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From: Frank Sae <Frank.Sae@motor-comm.com>
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Date: Thu, 2 Feb 2023 11:00:36 +0800
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Subject: [PATCH] net: phy: Add dts support for Motorcomm yt8531s gigabit
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ethernet phy
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Add dts support for Motorcomm yt8531s gigabit ethernet phy.
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Change yt8521_probe to support clk config of yt8531s. Becase
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yt8521_probe does the things which yt8531s is needed, so
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removed yt8531s function.
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This patch has been verified on AM335x platform with yt8531s board.
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Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/motorcomm.c | 51 ++++++++++++++++++++-----------------
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1 file changed, 27 insertions(+), 24 deletions(-)
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--- a/drivers/net/phy/motorcomm.c
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+++ b/drivers/net/phy/motorcomm.c
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@@ -258,8 +258,6 @@
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#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3
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#define YT8531_SCR_CLK_SRC_REF_25M 4
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#define YT8531_SCR_CLK_SRC_SSC_25M 5
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-#define YT8531S_SYNCE_CFG_REG 0xA012
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-#define YT8531S_SCR_SYNCE_ENABLE BIT(6)
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/* Extended Register end */
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@@ -858,7 +856,32 @@ static int yt8521_probe(struct phy_devic
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return -EINVAL;
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}
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} else if (phydev->drv->phy_id == PHY_ID_YT8531S) {
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- return 0;
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+ switch (freq) {
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+ case YTPHY_DTS_OUTPUT_CLK_DIS:
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+ mask = YT8531_SCR_SYNCE_ENABLE;
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+ val = 0;
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+ break;
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+ case YTPHY_DTS_OUTPUT_CLK_25M:
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+ mask = YT8531_SCR_SYNCE_ENABLE |
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+ YT8531_SCR_CLK_SRC_MASK |
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+ YT8531_SCR_CLK_FRE_SEL_125M;
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+ val = YT8531_SCR_SYNCE_ENABLE |
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+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
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+ YT8531_SCR_CLK_SRC_REF_25M);
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+ break;
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+ case YTPHY_DTS_OUTPUT_CLK_125M:
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+ mask = YT8531_SCR_SYNCE_ENABLE |
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+ YT8531_SCR_CLK_SRC_MASK |
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+ YT8531_SCR_CLK_FRE_SEL_125M;
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+ val = YT8531_SCR_SYNCE_ENABLE |
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+ YT8531_SCR_CLK_FRE_SEL_125M |
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+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
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+ YT8531_SCR_CLK_SRC_PLL_125M);
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+ break;
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+ default:
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+ phydev_warn(phydev, "Freq err:%u\n", freq);
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+ return -EINVAL;
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+ }
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} else {
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phydev_warn(phydev, "PHY id err\n");
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return -EINVAL;
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@@ -869,26 +892,6 @@ static int yt8521_probe(struct phy_devic
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}
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/**
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- * yt8531s_probe() - read chip config then set suitable polling_mode
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- * @phydev: a pointer to a &struct phy_device
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- *
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- * returns 0 or negative errno code
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- */
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-static int yt8531s_probe(struct phy_device *phydev)
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-{
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- int ret;
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-
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- /* Disable SyncE clock output by default */
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- ret = ytphy_modify_ext_with_lock(phydev, YT8531S_SYNCE_CFG_REG,
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- YT8531S_SCR_SYNCE_ENABLE, 0);
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- if (ret < 0)
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- return ret;
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-
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- /* same as yt8521_probe */
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- return yt8521_probe(phydev);
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-}
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-
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-/**
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* ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
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* @phydev: a pointer to a &struct phy_device
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*
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@@ -1970,7 +1973,7 @@ static struct phy_driver motorcomm_phy_d
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PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
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.name = "YT8531S Gigabit Ethernet",
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.get_features = yt8521_get_features,
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- .probe = yt8531s_probe,
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+ .probe = yt8521_probe,
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.read_page = yt8521_read_page,
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.write_page = yt8521_write_page,
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.get_wol = ytphy_get_wol,
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