7c9644a7b5
Replace downstream bmips RAC fixes with upstream patches. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> [backport upstream patches] Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
112 lines
3.5 KiB
Diff
112 lines
3.5 KiB
Diff
From b95b30e50aed225d26e20737873ae2404941901c Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 20 Jun 2024 17:26:44 +0200
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Subject: [PATCH 3/4] mips: bmips: setup: make CBR address configurable
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Add support to provide CBR address from DT to handle broken
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SoC/Bootloader that doesn't correctly init it. This permits to use the
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RAC flush even in these condition.
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To provide a CBR address from DT, the property "brcm,bmips-cbr-reg"
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needs to be set in the "cpus" node. On DT init, this property presence
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will be checked and will set the bmips_cbr_addr value accordingly. Also
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bmips_rac_flush_disable will be set to false as RAC flush can be
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correctly supported.
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The CBR address from DT will overwrite the cached one and the
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one set in the CBR register will be ignored.
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Also the DT CBR address is validated on being outside DRAM window.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/bcm47xx/setup.c | 6 +++++-
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arch/mips/bcm63xx/setup.c | 6 +++++-
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arch/mips/bmips/setup.c | 30 ++++++++++++++++++++++++++++--
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3 files changed, 38 insertions(+), 4 deletions(-)
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--- a/arch/mips/bcm47xx/setup.c
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+++ b/arch/mips/bcm47xx/setup.c
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@@ -46,7 +46,11 @@
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#include <bcm47xx.h>
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#include <bcm47xx_board.h>
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-/* CBR addr doesn't change and we can cache it */
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+/*
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+ * CBR addr doesn't change and we can cache it.
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+ * For broken SoC/Bootloader CBR addr might also be provided via DT
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+ * with "brcm,bmips-cbr-reg" in the "cpus" node.
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+ */
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void __iomem *bmips_cbr_addr __read_mostly;
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union bcm47xx_bus bcm47xx_bus;
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--- a/arch/mips/bcm63xx/setup.c
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+++ b/arch/mips/bcm63xx/setup.c
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@@ -23,7 +23,11 @@
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#include <bcm63xx_io.h>
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#include <bcm63xx_gpio.h>
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-/* CBR addr doesn't change and we can cache it */
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+/*
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+ * CBR addr doesn't change and we can cache it.
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+ * For broken SoC/Bootloader CBR addr might also be provided via DT
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+ * with "brcm,bmips-cbr-reg" in the "cpus" node.
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+ */
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void __iomem *bmips_cbr_addr __read_mostly;
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void bcm63xx_machine_halt(void)
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--- a/arch/mips/bmips/setup.c
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+++ b/arch/mips/bmips/setup.c
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@@ -34,7 +34,11 @@
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#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
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#define BCM6328_TP1_DISABLED BIT(9)
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-/* CBR addr doesn't change and we can cache it */
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+/*
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+ * CBR addr doesn't change and we can cache it.
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+ * For broken SoC/Bootloader CBR addr might also be provided via DT
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+ * with "brcm,bmips-cbr-reg" in the "cpus" node.
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+ */
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void __iomem *bmips_cbr_addr __read_mostly;
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extern bool bmips_rac_flush_disable;
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@@ -208,13 +212,35 @@ void __init plat_mem_setup(void)
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void __init device_tree_init(void)
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{
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struct device_node *np;
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+ u32 addr;
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unflatten_and_copy_device_tree();
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/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
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np = of_find_node_by_name(NULL, "cpus");
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- if (np && of_get_available_child_count(np) <= 1)
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+ if (!np)
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+ return;
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+
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+ if (of_get_available_child_count(np) <= 1)
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bmips_smp_enabled = 0;
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+
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+ /* Check if DT provide a CBR address */
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+ if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr))
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+ goto exit;
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+
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+ /* Make sure CBR address is outside DRAM window */
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+ if (addr >= (u32)memblock_start_of_DRAM() &&
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+ addr < (u32)memblock_end_of_DRAM()) {
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+ WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n",
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+ addr);
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+ goto exit;
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+ }
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+
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+ bmips_cbr_addr = (void __iomem *)addr;
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+ /* Since CBR is provided by DT, enable RAC flush */
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+ bmips_rac_flush_disable = false;
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+
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+exit:
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of_node_put(np);
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}
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