6bbb75dfdc
bmips has all the dt-bindings includes inside each SoC .dtsi files, so let's move the new includes there instead of adding them to each board .dts files. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
189 lines
2.8 KiB
Plaintext
189 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "bcm6328.dtsi"
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/ {
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model = "Arcadyan AR7516";
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compatible = "arcadyan,ar7516", "brcm,bcm6328";
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aliases {
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led-failsafe = &led_upgrade_green;
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led-upgrade = &led_upgrade_green;
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <100>;
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reset {
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label = "reset";
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gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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debounce-interval = <60>;
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};
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wps {
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label = "wps";
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gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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debounce-interval = <60>;
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};
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};
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bcm43227-sprom {
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compatible = "brcm,bcma-sprom";
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pci-bus = <1>;
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pci-dev = <0>;
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nvmem-cells = <&macaddr_cfe_6a0 1>;
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nvmem-cell-names = "mac-address";
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brcm,sprom = "brcm/bcm43227-sprom.bin";
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};
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};
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&ehci {
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status = "okay";
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};
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ðernet {
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status = "okay";
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nvmem-cells = <&macaddr_cfe_6a0 0>;
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nvmem-cell-names = "mac-address";
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};
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&hsspi {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <16666667>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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reg = <0>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "cfe";
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reg = <0x000000 0x010000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_cfe_6a0: macaddr@6a0 {
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compatible = "mac-base";
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reg = <0x6a0 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@10000 {
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compatible = "brcm,bcm963xx-imagetag";
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label = "firmware";
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reg = <0x010000 0x7e0000>;
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};
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partition@7f0000 {
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label = "nvram";
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reg = <0x7f0000 0x010000>;
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};
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};
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};
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};
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&leds {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ephy0_act_led &pinctrl_ephy1_act_led
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&pinctrl_ephy2_act_led &pinctrl_ephy3_act_led
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&pinctrl_leds>;
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led_upgrade_green: led@1 {
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reg = <1>;
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label = "green:upgrade";
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};
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led@6 {
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reg = <6>;
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active-low;
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function = LED_FUNCTION_WAN;
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color = <LED_COLOR_ID_GREEN>;
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};
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led@7 {
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reg = <7>;
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active-low;
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label = "green:wifi";
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};
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};
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&ohci {
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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&pinctrl {
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pinctrl_leds: leds {
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function = "led";
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pins = "gpio1", "gpio6", "gpio7";
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};
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};
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&switch0 {
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ports {
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port@0 {
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reg = <0>;
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label = "lan1";
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phy-handle = <&phy1>;
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phy-mode = "mii";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-handle = <&phy2>;
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phy-mode = "mii";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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phy-handle = <&phy3>;
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phy-mode = "mii";
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};
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port@3 {
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reg = <3>;
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label = "wan";
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phy-handle = <&phy4>;
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phy-mode = "mii";
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&usbh {
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status = "okay";
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};
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