8619d7af67
Dual-slot NAS based on Marvell Kirkwood. Specifications: - Marvell 88F6702 @1GHz - 256Mb RAM - 128Mb NAND - 1x GbE LAN (Marvell 88E1318R) - 1x USB 2.0 - 2x SATA - Weltrend WT69P3 ("supervisor" MCU chip) - Serial on J2 (115200,8n1) - Newer bootROM so kwboot-ing via serial is possible Notes: - The Weltrend MCU is controlled by the package added in utils/dns320l-mcu. - The original MAC address is stored in the "mini firmware" image's first 17 bytes. - Compared to the original MTD layout, the uImage+rootfs are now stored in a common ubi partition. Installation: 1. Serial console - Connect your levelshifter to the serial console on J2 (refer to the wiki page for pinout) 2. Update u-boot - Download the u-boot.kwb image for the device - Powercycle the NAS - Run "kwboot -b u-boot-dns320l/u-boot.kwb /dev/ttyUSB0 -p" - Connect to the serial console with minicom - tftp 0x0800000 u-boot-dns320l/u-boot.kwb (Please note that "PHY reset timed out" seems to be customary on kirkwood devices, the egiga0 interface works regardless.) - nand erase 0x0 100000 - nand write 0x0800000 0x0 0x100000 - reset 3. Install OpenWrt - Boot up the initramfs image - tftpboot 0x800000 openwrt-kirkwood-generic-dlink_dns320l-initramfs-uImage; bootm 0x800000 - Download the sysupgrade image and perform sysupgrade Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> Reviewed-by: Pawel Dembicki <paweldembicki@gmail.com>
388 lines
9.3 KiB
Diff
388 lines
9.3 KiB
Diff
--- a/arch/arm/mach-kirkwood/Kconfig
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+++ b/arch/arm/mach-kirkwood/Kconfig
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@@ -28,6 +28,9 @@ config TARGET_POGO_E02
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config TARGET_POGOPLUGV4
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bool "Pogoplug V4 Board"
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+config TARGET_DNS320L
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+ bool "dns320l Board"
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+
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config TARGET_DNS325
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bool "dns325 Board"
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@@ -93,6 +96,7 @@ source "board/Marvell/sheevaplug/Kconfig
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source "board/buffalo/lsxl/Kconfig"
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source "board/cloudengines/pogo_e02/Kconfig"
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source "board/cloudengines/pogoplugv4/Kconfig"
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+source "board/d-link/dns320l/Kconfig"
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source "board/d-link/dns325/Kconfig"
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source "board/iomega/iconnect/Kconfig"
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source "board/keymile/Kconfig"
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--- /dev/null
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+++ b/board/d-link/dns320l/dns320l.c
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@@ -0,0 +1,113 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2015
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+ * Gerald Kerma <dreagle@doukki.net>
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+ * Tony Dinh <mibodhi@gmail.com>
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+ */
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+
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+#include <common.h>
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+#include <miiphy.h>
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+#include <net.h>
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+#include <asm/arch/cpu.h>
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+#include <asm/arch/soc.h>
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+#include <asm/arch/mpp.h>
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+#include <asm/arch/gpio.h>
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+#include <asm/io.h>
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+#include "dns320l.h"
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+int board_early_init_f(void)
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+{
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+ /*
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+ * default gpio configuration
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+ * There are maximum 64 gpios controlled through 2 sets of registers
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+ * the below configuration configures mainly initial LED status
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+ */
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+ mvebu_config_gpio(DNS320L_OE_VAL_LOW, DNS320L_OE_VAL_HIGH,
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+ DNS320L_OE_LOW, DNS320L_OE_HIGH);
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+
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+ /* (all LEDs & power off active high) */
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+ /* Multi-Purpose Pins Functionality configuration */
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+ static const u32 kwmpp_config[] = {
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+ MPP0_NF_IO2,
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+ MPP1_NF_IO3,
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+ MPP2_NF_IO4,
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+ MPP3_NF_IO5,
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+ MPP4_NF_IO6,
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+ MPP5_NF_IO7,
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+ MPP6_SYSRST_OUTn,
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+ MPP7_GPO,
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+ MPP8_TW_SDA,
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+ MPP9_TW_SCK,
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+ MPP10_UART0_TXD,
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+ MPP11_UART0_RXD,
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+ MPP12_GPO,
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+ MPP13_GPIO,
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+ MPP14_GPIO,
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+ MPP15_GPIO,
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+ MPP16_GPIO,
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+ MPP17_GPIO,
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+ MPP18_NF_IO0,
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+ MPP19_NF_IO1,
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+ MPP20_SATA1_ACTn, /* sata1(left) status led */
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+ MPP21_SATA0_ACTn, /* sata0(right) status led */
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+ MPP22_GPIO,
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+ MPP23_GPIO,
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+ MPP24_GPIO,
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+ MPP25_GPIO,
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+ MPP26_GPIO,
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+ MPP27_GPIO,
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+ MPP28_GPIO,
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+ MPP29_GPIO,
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+ MPP30_GPIO,
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+ MPP31_GPIO,
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+ MPP32_GPIO,
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+ 0
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+ };
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+ kirkwood_mpp_conf(kwmpp_config, NULL);
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+
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+ kw_gpio_set_value(DNS320L_GPIO_SATA_EN , 1);
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+
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+ return 0;
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+}
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+
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+int board_init(void)
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+{
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+ /* address of boot parameters */
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+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_RESET_PHY_R
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+/* Configure and initialize PHY */
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+void reset_phy(void)
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+{
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+ u16 reg;
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+ u16 phyaddr;
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+ char *name = "egiga0";
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+
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+ if (miiphy_set_current_dev(name))
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+ return;
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+
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+ /* read PHY dev address */
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+ if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
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+ printf("could not read PHY dev address\n");
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+ return;
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+ }
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+
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+ /* set RGMII delay */
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+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
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+ miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
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+ reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
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+ miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
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+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
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+
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+ /* reset PHY */
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+ if (miiphy_reset(name, phyaddr))
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+ return;
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+
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+ printf("MV88E1318 PHY initialized on %s\n", name);
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+}
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+#endif /* CONFIG_RESET_PHY_R */
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--- /dev/null
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+++ b/board/d-link/dns320l/dns320l.h
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@@ -0,0 +1,39 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+/*
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+ * Copyright (C) 2011
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+ * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
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+ *
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+ * Based on Kirkwood support:
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+ * (C) Copyright 2009
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+ * Marvell Semiconductor <www.marvell.com>
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+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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+ */
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+
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+#ifndef __DNS320L_H
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+#define __DNS320L_H
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+
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+/* GPIO configuration */
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+#define DNS320L_GPIO_SATA_EN 24
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+#define HDD_L_GREEN_LED (1 << 22)
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+#define HDD_R_GREEN_LED (1 << 23)
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+#define USB_BLUE_LED (1 << 25)
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+#define USB_ORANGE_LED (1 << 26)
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+
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+#define DNS320L_OE_LOW (~(HDD_L_GREEN_LED | HDD_R_GREEN_LED | \
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+ USB_BLUE_LED | USB_ORANGE_LED))
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+#define DNS320L_OE_VAL_LOW (0)
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+
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+/* high GPIO's */
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+#define WATCHDOG_SIGNAL (1 << 14)
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+
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+#define DNS320L_OE_HIGH (~(WATCHDOG_SIGNAL))
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+#define DNS320L_OE_VAL_HIGH ((WATCHDOG_SIGNAL))
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+
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+/* PHY related */
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+#define MV88E1318_PGADR_REG 22
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+#define MV88E1318_MAC_CTRL_PG 2
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+#define MV88E1318_MAC_CTRL_REG 21
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+#define MV88E1318_RGMII_TX_CTRL (1 << 4)
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+#define MV88E1318_RGMII_RX_CTRL (1 << 5)
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+
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+#endif /* __DNS320L_H */
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--- /dev/null
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+++ b/board/d-link/dns320l/Kconfig
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@@ -0,0 +1,18 @@
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+# Copyright (C) 2015
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+# Gerald Kerma <dreagle@doukki.net>
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+# Tony Dinh <mibodhi@gmail.com>
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+
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+if TARGET_DNS320L
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+
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+config SYS_BOARD
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+ default "dns320l"
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+
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+config SYS_VENDOR
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+ default "d-link"
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+
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+config SYS_CONFIG_NAME
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+ default "dns320l"
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+
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+endif
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--- /dev/null
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+++ b/board/d-link/dns320l/kwbimage.cfg
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@@ -0,0 +1,41 @@
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+# Copyright (C) 2015
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+# Gerald Kerma <dreagle@doukki.net>
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+# Tony Dinh <mibodhi@gmail.com>
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+# Refer to doc/README.kwbimage for more details about how-to
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+# configure and create kirkwood boot images.
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+#
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+
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+# Boot Media configurations
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+BOOT_FROM nand
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+NAND_ECC_MODE default
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+NAND_PAGE_SIZE 0x0800
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+
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+# Configure RGMII-0 interface pad voltage to 1.8V
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+DATA 0xFFD100e0 0x1b1b1b9b
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+
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+DATA 0xFFD01400 0x43010c30
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+DATA 0xFFD01404 0x39543000
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+DATA 0xFFD01408 0x22125451
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+DATA 0xFFD0140C 0x00000833
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+DATA 0xFFD01410 0x0000000C
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+DATA 0xFFD01414 0x00000000
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+DATA 0xFFD01418 0x00000000
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+DATA 0xFFD0141C 0x00000652
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+DATA 0xFFD01420 0x00000004
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+DATA 0xFFD01424 0x0000F17F
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+DATA 0xFFD01428 0x00085520
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+DATA 0xFFD0147c 0x00008552
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+DATA 0xFFD01504 0x0FFFFFF1
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+DATA 0xFFD01508 0x10000000
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+DATA 0xFFD0150C 0x00000000
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+DATA 0xFFD01514 0x00000000
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+DATA 0xFFD0151C 0x00000000
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+DATA 0xFFD01494 0x00010000
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+DATA 0xFFD01498 0x00000000
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+DATA 0xFFD0149C 0x0000E403
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+DATA 0xFFD01480 0x00000001
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+DATA 0xFFD20134 0x66666666
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+DATA 0xFFD20138 0x66666666
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+DATA 0x0 0x0
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--- /dev/null
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+++ b/board/d-link/dns320l/MAINTAINERS
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@@ -0,0 +1,8 @@
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+NSA310S BOARD
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+M: Gerald Kerma <dreagle@doukki.net>
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+M: Tony Dinh <mibodhi@gmail.com>
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+M: Luka Perkov <luka.perkov@sartura.hr>
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+S: Maintained
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+F: board/d-link/dns320l/
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+F: include/configs/dns320l.h
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+F: configs/dns320l_defconfig
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--- /dev/null
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+++ b/board/d-link/dns320l/Makefile
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@@ -0,0 +1,7 @@
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+# Copyright (C) 2015
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+# Gerald Kerma <dreagle@doukki.net>
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+# Tony Dinh <mibodhi@gmail.com>
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+
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+obj-y := dns320l.o
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--- /dev/null
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+++ b/configs/dns320l_defconfig
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@@ -0,0 +1,48 @@
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+CONFIG_ARM=y
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+CONFIG_SYS_DCACHE_OFF=y
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+CONFIG_ARCH_CPU_INIT=y
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+CONFIG_KIRKWOOD=y
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+CONFIG_SYS_TEXT_BASE=0x600000
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+CONFIG_TARGET_DNS320L=y
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+CONFIG_ENV_SIZE=0x20000
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+CONFIG_ENV_OFFSET=0x100000
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+CONFIG_NR_DRAM_BANKS=2
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+CONFIG_BOOTDELAY=3
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+CONFIG_USE_PREBOOT=y
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+# CONFIG_DISPLAY_BOARDINFO is not set
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+CONFIG_HUSH_PARSER=y
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+CONFIG_SYS_PROMPT="dns320l => "
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+CONFIG_CMD_BOOTZ=y
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+# CONFIG_CMD_FLASH is not set
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+CONFIG_CMD_IDE=y
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+CONFIG_CMD_NAND=y
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+CONFIG_CMD_USB=y
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+# CONFIG_CMD_SETEXPR is not set
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+CONFIG_CMD_DHCP=y
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+CONFIG_CMD_MII=y
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+CONFIG_CMD_PING=y
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+CONFIG_CMD_EXT2=y
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+CONFIG_CMD_FAT=y
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+CONFIG_CMD_JFFS2=y
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+CONFIG_CMD_MTDPARTS=y
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+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000@0x0(uboot),0x20000@0x100000(ubootenv),0x6de0000@0x120000(ubi),0xa00000@0x6f00000(mini),0x500000@0x7900000(config),0x200000@0x7e00000(my-dlink)"
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+CONFIG_CMD_UBI=y
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+CONFIG_ISO_PARTITION=y
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+CONFIG_ENV_IS_IN_NAND=y
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+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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+CONFIG_MVSATA_IDE=y
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+# CONFIG_MMC is not set
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+CONFIG_MTD=y
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+CONFIG_MTD_RAW_NAND=y
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+CONFIG_MVGBE=y
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+CONFIG_MII=y
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+CONFIG_SYS_NS16550=y
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+CONFIG_USB=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_STORAGE=y
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_LZMA=y
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+CONFIG_LZO=y
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+CONFIG_OF_LIBFDT=y
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+CONFIG_NET_RANDOM_ETHADDR=y
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--- /dev/null
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+++ b/include/configs/dns320l.h
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@@ -0,0 +1,69 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+/*
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+ * Copyright (C) 2015
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+ * Gerald Kerma <dreagle@doukki.net>
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+ * Tony Dinh <mibodhi@gmail.com>
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+ * Luka Perkov <luka.perkov@sartura.hr>
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+ */
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+
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+#ifndef _CONFIG_DNS320L_H
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+#define _CONFIG_DNS320L_H
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+
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+/* high level configuration options */
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+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
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+#define CONFIG_KW88F6192 1 /* SOC Name */
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+#define CONFIG_KW88F6702 1 /* SOC Name */
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+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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+
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+/* compression configuration */
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+#define CONFIG_BZIP2
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+
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+/* commands configuration */
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+
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+/*
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+ * mv-common.h should be defined after CMD configs since it used them
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+ * to enable certain macros
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+ */
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+#include "mv-common.h"
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+
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+/* environment variables configuration */
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+
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+/* default environment variables */
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+#define CONFIG_BOOTCOMMAND \
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+ "ubi part ubi; " \
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+ "ubi read 0x800000 kernel; " \
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+ "bootm 0x800000"
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+
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+#define CONFIG_EXTRA_ENV_SETTINGS \
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+ "console=console=ttyS0,115200\0" \
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+ "mtdids=nand0=orion_nand\0" \
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+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
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+ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
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+
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+/* Ethernet driver configuration */
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+#ifdef CONFIG_CMD_NET
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+#define CONFIG_NETCONSOLE
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+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
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+#define CONFIG_PHY_BASE_ADR 1
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+#define CONFIG_RESET_PHY_R
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+#endif /* CONFIG_CMD_NET */
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+
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+/* SATA driver configuration */
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+#ifdef CONFIG_IDE
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+#define __io
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+#define CONFIG_IDE_PREINIT
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+#define CONFIG_MVSATA_IDE_USE_PORT0
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+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
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+#endif /* CONFIG_IDE */
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+
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+/*
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+ * Enable GPI0 support
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+*/
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+#define CONFIG_KIRKWOOD_GPIO
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+
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+/* RTC driver configuration */
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+#ifdef CONFIG_CMD_DATE
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+#define CONFIG_RTC_MV
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+#endif /* CONFIG_CMD_DATE */
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+
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+#endif /* _CONFIG_DNS320L_H */
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