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kernel-49/sound/soc/codecs/cs53l30.c
Eric Biggers cb74d5c7ab Merge 4.9.320 into android-4.9-q 
Changes in 4.9.320
	9p: missing chunk of "fs/9p: Don't update file type when updating file attributes"
	random: remove stale maybe_reseed_primary_crng
	random: remove stale urandom_init_wait
	random: remove variable limit
	random: fix comment for unused random_min_urandom_seed
	random: convert get_random_int/long into get_random_u32/u64
	random: move random_min_urandom_seed into CONFIG_SYSCTL ifdef block
	random: invalidate batched entropy after crng init
	random: silence compiler warnings and fix race
	random: add wait_for_random_bytes() API
	random: add get_random_{bytes,u32,u64,int,long,once}_wait family
	random: warn when kernel uses unseeded randomness
	random: do not ignore early device randomness
	random: suppress spammy warnings about unseeded randomness
	random: reorder READ_ONCE() in get_random_uXX
	random: fix warning message on ia64 and parisc
	random: use a different mixing algorithm for add_device_randomness()
	random: set up the NUMA crng instances after the CRNG is fully initialized
	random: fix possible sleeping allocation from irq context
	random: rate limit unseeded randomness warnings
	random: add a spinlock_t to struct batched_entropy
	char/random: silence a lockdep splat with printk()
	Revert "char/random: silence a lockdep splat with printk()"
	random: always use batched entropy for get_random_u{32,64}
	random: fix data race on crng_node_pool
	crypto: chacha20 - Fix keystream alignment for chacha20_block()
	random: always fill buffer in get_random_bytes_wait
	random: optimize add_interrupt_randomness
	drivers/char/random.c: remove unused dont_count_entropy
	random: Fix whitespace pre random-bytes work
	random: Return nbytes filled from hw RNG
	random: add a config option to trust the CPU's hwrng
	random: remove preempt disabled region
	random: Make crng state queryable
	random: make CPU trust a boot parameter
	drivers/char/random.c: constify poolinfo_table
	drivers/char/random.c: remove unused stuct poolinfo::poolbits
	drivers/char/random.c: make primary_crng static
	random: only read from /dev/random after its pool has received 128 bits
	random: move rand_initialize() earlier
	random: document get_random_int() family
	latent_entropy: avoid build error when plugin cflags are not set
	random: fix soft lockup when trying to read from an uninitialized blocking pool
	random: Support freezable kthreads in add_hwgenerator_randomness()
	fdt: add support for rng-seed
	random: Use wait_event_freezable() in add_hwgenerator_randomness()
	char/random: Add a newline at the end of the file
	Revert "hwrng: core - Freeze khwrng thread during suspend"
	crypto: Deduplicate le32_to_cpu_array() and cpu_to_le32_array()
	crypto: blake2s - generic C library implementation and selftest
	lib/crypto: blake2s: move hmac construction into wireguard
	lib/crypto: sha1: re-roll loops to reduce code size
	random: Don't wake crng_init_wait when crng_init == 1
	random: Add a urandom_read_nowait() for random APIs that don't warn
	random: add GRND_INSECURE to return best-effort non-cryptographic bytes
	random: ignore GRND_RANDOM in getentropy(2)
	random: make /dev/random be almost like /dev/urandom
	random: fix crash on multiple early calls to add_bootloader_randomness()
	random: remove the blocking pool
	random: delete code to pull data into pools
	random: remove kernel.random.read_wakeup_threshold
	random: remove unnecessary unlikely()
	random: convert to ENTROPY_BITS for better code readability
	random: Add and use pr_fmt()
	random: fix typo in add_timer_randomness()
	random: remove some dead code of poolinfo
	random: split primary/secondary crng init paths
	random: avoid warnings for !CONFIG_NUMA builds
	x86: Remove arch_has_random, arch_has_random_seed
	powerpc: Remove arch_has_random, arch_has_random_seed
	linux/random.h: Remove arch_has_random, arch_has_random_seed
	linux/random.h: Use false with bool
	linux/random.h: Mark CONFIG_ARCH_RANDOM functions __must_check
	powerpc: Use bool in archrandom.h
	random: add arch_get_random_*long_early()
	random: avoid arch_get_random_seed_long() when collecting IRQ randomness
	random: remove dead code left over from blocking pool
	MAINTAINERS: co-maintain random.c
	crypto: blake2s - include <linux/bug.h> instead of <asm/bug.h>
	crypto: blake2s - adjust include guard naming
	random: document add_hwgenerator_randomness() with other input functions
	random: remove unused irq_flags argument from add_interrupt_randomness()
	random: use BLAKE2s instead of SHA1 in extraction
	random: do not sign extend bytes for rotation when mixing
	random: do not re-init if crng_reseed completes before primary init
	random: mix bootloader randomness into pool
	random: harmonize "crng init done" messages
	random: use IS_ENABLED(CONFIG_NUMA) instead of ifdefs
	random: initialize ChaCha20 constants with correct endianness
	random: early initialization of ChaCha constants
	random: avoid superfluous call to RDRAND in CRNG extraction
	random: don't reset crng_init_cnt on urandom_read()
	random: fix typo in comments
	random: cleanup poolinfo abstraction
	crypto: chacha20 - Fix chacha20_block() keystream alignment (again)
	random: cleanup integer types
	random: remove incomplete last_data logic
	random: remove unused extract_entropy() reserved argument
	random: try to actively add entropy rather than passively wait for it
	random: rather than entropy_store abstraction, use global
	random: remove unused OUTPUT_POOL constants
	random: de-duplicate INPUT_POOL constants
	random: prepend remaining pool constants with POOL_
	random: cleanup fractional entropy shift constants
	random: access input_pool_data directly rather than through pointer
	random: simplify arithmetic function flow in account()
	random: continually use hwgenerator randomness
	random: access primary_pool directly rather than through pointer
	random: only call crng_finalize_init() for primary_crng
	random: use computational hash for entropy extraction
	random: simplify entropy debiting
	random: use linear min-entropy accumulation crediting
	random: always wake up entropy writers after extraction
	random: make credit_entropy_bits() always safe
	random: remove use_input_pool parameter from crng_reseed()
	random: remove batched entropy locking
	random: fix locking in crng_fast_load()
	random: use RDSEED instead of RDRAND in entropy extraction
	random: inline leaves of rand_initialize()
	random: ensure early RDSEED goes through mixer on init
	random: do not xor RDRAND when writing into /dev/random
	random: absorb fast pool into input pool after fast load
	random: use hash function for crng_slow_load()
	random: remove outdated INT_MAX >> 6 check in urandom_read()
	random: zero buffer after reading entropy from userspace
	random: tie batched entropy generation to base_crng generation
	random: remove ifdef'd out interrupt bench
	random: remove unused tracepoints
	random: add proper SPDX header
	random: deobfuscate irq u32/u64 contributions
	random: introduce drain_entropy() helper to declutter crng_reseed()
	random: remove useless header comment
	random: remove whitespace and reorder includes
	random: group initialization wait functions
	random: group entropy extraction functions
	random: group entropy collection functions
	random: group userspace read/write functions
	random: group sysctl functions
	random: rewrite header introductory comment
	workqueue: make workqueue available early during boot
	random: defer fast pool mixing to worker
	random: do not take pool spinlock at boot
	random: unify early init crng load accounting
	random: check for crng_init == 0 in add_device_randomness()
	hwrng: core - do not use multiple blank lines
	hwrng: core - rewrite better comparison to NULL
	hwrng: core - Rewrite the header
	hwrng: core - Move hwrng miscdev minor number to include/linux/miscdevice.h
	hwrng: core - remove unused PFX macro
	hwrng: use rng source with best quality
	hwrng: remember rng chosen by user
	random: pull add_hwgenerator_randomness() declaration into random.h
	random: clear fast pool, crng, and batches in cpuhp bring up
	random: round-robin registers as ulong, not u32
	random: only wake up writers after zap if threshold was passed
	random: cleanup UUID handling
	random: unify cycles_t and jiffies usage and types
	random: do crng pre-init loading in worker rather than irq
	random: give sysctl_random_min_urandom_seed a more sensible value
	random: don't let 644 read-only sysctls be written to
	random: replace custom notifier chain with standard one
	random: use SipHash as interrupt entropy accumulator
	random: make consistent usage of crng_ready()
	random: reseed more often immediately after booting
	random: check for signal and try earlier when generating entropy
	random: skip fast_init if hwrng provides large chunk of entropy
	random: treat bootloader trust toggle the same way as cpu trust toggle
	random: re-add removed comment about get_random_{u32,u64} reseeding
	random: mix build-time latent entropy into pool at init
	random: do not split fast init input in add_hwgenerator_randomness()
	random: do not allow user to keep crng key around on stack
	random: check for signal_pending() outside of need_resched() check
	random: check for signals every PAGE_SIZE chunk of /dev/[u]random
	random: make random_get_entropy() return an unsigned long
	random: document crng_fast_key_erasure() destination possibility
	random: fix sysctl documentation nits
	init: call time_init() before rand_initialize()
	ia64: define get_cycles macro for arch-override
	s390: define get_cycles macro for arch-override
	parisc: define get_cycles macro for arch-override
	alpha: define get_cycles macro for arch-override
	powerpc: define get_cycles macro for arch-override
	timekeeping: Add raw clock fallback for random_get_entropy()
	m68k: use fallback for random_get_entropy() instead of zero
	mips: use fallback for random_get_entropy() instead of just c0 random
	arm: use fallback for random_get_entropy() instead of zero
	nios2: use fallback for random_get_entropy() instead of zero
	x86/tsc: Use fallback for random_get_entropy() instead of zero
	um: use fallback for random_get_entropy() instead of zero
	sparc: use fallback for random_get_entropy() instead of zero
	xtensa: use fallback for random_get_entropy() instead of zero
	uapi: rename ext2_swab() to swab() and share globally in swab.h
	random: insist on random_get_entropy() existing in order to simplify
	random: do not use batches when !crng_ready()
	random: do not pretend to handle premature next security model
	random: order timer entropy functions below interrupt functions
	random: do not use input pool from hard IRQs
	random: help compiler out with fast_mix() by using simpler arguments
	siphash: use one source of truth for siphash permutations
	random: use symbolic constants for crng_init states
	random: avoid initializing twice in credit race
	random: remove ratelimiting for in-kernel unseeded randomness
	random: use proper jiffies comparison macro
	random: handle latent entropy and command line from random_init()
	random: credit architectural init the exact amount
	random: use static branch for crng_ready()
	random: remove extern from functions in header
	random: use proper return types on get_random_{int,long}_wait()
	random: move initialization functions out of hot pages
	random: move randomize_page() into mm where it belongs
	random: convert to using fops->write_iter()
	random: wire up fops->splice_{read,write}_iter()
	random: check for signals after page of pool writes
	Revert "random: use static branch for crng_ready()"
	crypto: drbg - add FIPS 140-2 CTRNG for noise source
	crypto: drbg - always seeded with SP800-90B compliant noise source
	crypto: drbg - prepare for more fine-grained tracking of seeding state
	crypto: drbg - track whether DRBG was seeded with !rng_is_initialized()
	crypto: drbg - move dynamic ->reseed_threshold adjustments to __drbg_seed()
	crypto: drbg - always try to free Jitter RNG instance
	crypto: drbg - make reseeding from get_random_bytes() synchronous
	random: avoid checking crng_ready() twice in random_init()
	random: mark bootloader randomness code as __init
	random: account for arch randomness in bits
	ASoC: cs42l52: Fix TLV scales for mixer controls
	ASoC: cs53l30: Correct number of volume levels on SX controls
	ASoC: cs42l52: Correct TLV for Bypass Volume
	ASoC: cs42l56: Correct typo in minimum level for SX volume controls
	ata: libata-core: fix NULL pointer deref in ata_host_alloc_pinfo()
	ASoC: wm8962: Fix suspend while playing music
	scsi: vmw_pvscsi: Expand vcpuHint to 16 bits
	scsi: lpfc: Fix port stuck in bypassed state after LIP in PT2PT topology
	virtio-mmio: fix missing put_device() when vm_cmdline_parent registration failed
	nfc: nfcmrvl: Fix memory leak in nfcmrvl_play_deferred
	ipv6: Fix signed integer overflow in l2tp_ip6_sendmsg
	net: ethernet: mtk_eth_soc: fix misuse of mem alloc interface netdev[napi]_alloc_frag
	random: credit cpu and bootloader seeds by default
	pNFS: Don't keep retrying if the server replied NFS4ERR_LAYOUTUNAVAILABLE
	misc: atmel-ssc: Fix IRQ check in ssc_probe
	irqchip/gic/realview: Fix refcount leak in realview_gic_of_init
	irqchip/gic-v3: Iterate over possible CPUs by for_each_possible_cpu()
	comedi: vmk80xx: fix expression for tx buffer size
	USB: serial: option: add support for Cinterion MV31 with new baseline
	USB: serial: io_ti: add Agilent E5805A support
	usb: gadget: lpc32xx_udc: Fix refcount leak in lpc32xx_udc_probe
	serial: 8250: Store to lsr_save_flags after lsr read
	ext4: fix bug_on ext4_mb_use_inode_pa
	ext4: make variable "count" signed
	ext4: add reserved GDT blocks check
	l2tp: don't use inet_shutdown on ppp session destroy
	l2tp: fix race in pppol2tp_release with session object destroy
	s390/mm: use non-quiescing sske for KVM switch to keyed guest
	xprtrdma: fix incorrect header size calculations
	swiotlb: fix info leak with DMA_FROM_DEVICE
	Reinstate some of "swiotlb: rework "fix info leak with DMA_FROM_DEVICE""
	fuse: fix pipe buffer lifetime for direct_io
	tcp: change source port randomizarion at connect() time
	tcp: add some entropy in __inet_hash_connect()
	secure_seq: use the 64 bits of the siphash for port offset calculation
	tcp: use different parts of the port_offset for index and offset
	tcp: add small random increments to the source port
	tcp: dynamically allocate the perturb table used by source ports
	tcp: increase source port perturb table to 2^16
	tcp: drop the hash_32() part from the index calculation
	Linux 4.9.320

Conflicts:
	crypto/chacha20_generic.c
	drivers/char/random.c
	drivers/of/fdt.c
	include/crypto/chacha20.h
	lib/chacha20.c

Merge resolution notes:
  - Added CHACHA20_KEY_SIZE and CHACHA20_BLOCK_SIZE constants to
    chacha.h, to minimize changes from the 4.9.320 version of random.c

  - Updated lib/vsprintf.c for
    "random: replace custom notifier chain with standard one".

Change-Id: Ia7a12d8883b808f88bbe807d6150552bb084f6b3
Signed-off-by: Eric Biggers <ebiggers@google.com>
2022-07-04 10:26:10 +03:00

1145 lines
34 KiB
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/*
* cs53l30.c -- CS53l30 ALSA Soc Audio driver
*
* Copyright 2015 Cirrus Logic, Inc.
*
* Authors: Paul Handrigan <Paul.Handrigan@cirrus.com>,
* Tim Howe <Tim.Howe@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "cs53l30.h"
#define CS53L30_NUM_SUPPLIES 2
static const char *const cs53l30_supply_names[CS53L30_NUM_SUPPLIES] = {
"VA",
"VP",
};
struct cs53l30_private {
struct regulator_bulk_data supplies[CS53L30_NUM_SUPPLIES];
struct regmap *regmap;
struct gpio_desc *reset_gpio;
struct gpio_desc *mute_gpio;
struct clk *mclk;
bool use_sdout2;
u32 mclk_rate;
};
static const struct reg_default cs53l30_reg_defaults[] = {
{ CS53L30_PWRCTL, CS53L30_PWRCTL_DEFAULT },
{ CS53L30_MCLKCTL, CS53L30_MCLKCTL_DEFAULT },
{ CS53L30_INT_SR_CTL, CS53L30_INT_SR_CTL_DEFAULT },
{ CS53L30_MICBIAS_CTL, CS53L30_MICBIAS_CTL_DEFAULT },
{ CS53L30_ASPCFG_CTL, CS53L30_ASPCFG_CTL_DEFAULT },
{ CS53L30_ASP_CTL1, CS53L30_ASP_CTL1_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL1, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL2, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL3, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_CTL4, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN1, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN2, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN3, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN4, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN5, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_TDMTX_EN6, CS53L30_ASP_TDMTX_ENx_DEFAULT },
{ CS53L30_ASP_CTL2, CS53L30_ASP_CTL2_DEFAULT },
{ CS53L30_SFT_RAMP, CS53L30_SFT_RMP_DEFAULT },
{ CS53L30_LRCK_CTL1, CS53L30_LRCK_CTLx_DEFAULT },
{ CS53L30_LRCK_CTL2, CS53L30_LRCK_CTLx_DEFAULT },
{ CS53L30_MUTEP_CTL1, CS53L30_MUTEP_CTL1_DEFAULT },
{ CS53L30_MUTEP_CTL2, CS53L30_MUTEP_CTL2_DEFAULT },
{ CS53L30_INBIAS_CTL1, CS53L30_INBIAS_CTL1_DEFAULT },
{ CS53L30_INBIAS_CTL2, CS53L30_INBIAS_CTL2_DEFAULT },
{ CS53L30_DMIC1_STR_CTL, CS53L30_DMIC1_STR_CTL_DEFAULT },
{ CS53L30_DMIC2_STR_CTL, CS53L30_DMIC2_STR_CTL_DEFAULT },
{ CS53L30_ADCDMIC1_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
{ CS53L30_ADCDMIC1_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
{ CS53L30_ADC1_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
{ CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
{ CS53L30_ADC1A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC1A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADC1B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADCDMIC2_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
{ CS53L30_ADCDMIC2_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
{ CS53L30_ADC2_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
{ CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
{ CS53L30_ADC2A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
{ CS53L30_ADC2A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_ADC2B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
{ CS53L30_INT_MASK, CS53L30_DEVICE_INT_MASK },
};
static bool cs53l30_volatile_register(struct device *dev, unsigned int reg)
{
if (reg == CS53L30_IS)
return true;
else
return false;
}
static bool cs53l30_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS53L30_DEVID_AB:
case CS53L30_DEVID_CD:
case CS53L30_DEVID_E:
case CS53L30_REVID:
case CS53L30_IS:
return false;
default:
return true;
}
}
static bool cs53l30_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS53L30_DEVID_AB:
case CS53L30_DEVID_CD:
case CS53L30_DEVID_E:
case CS53L30_REVID:
case CS53L30_PWRCTL:
case CS53L30_MCLKCTL:
case CS53L30_INT_SR_CTL:
case CS53L30_MICBIAS_CTL:
case CS53L30_ASPCFG_CTL:
case CS53L30_ASP_CTL1:
case CS53L30_ASP_TDMTX_CTL1:
case CS53L30_ASP_TDMTX_CTL2:
case CS53L30_ASP_TDMTX_CTL3:
case CS53L30_ASP_TDMTX_CTL4:
case CS53L30_ASP_TDMTX_EN1:
case CS53L30_ASP_TDMTX_EN2:
case CS53L30_ASP_TDMTX_EN3:
case CS53L30_ASP_TDMTX_EN4:
case CS53L30_ASP_TDMTX_EN5:
case CS53L30_ASP_TDMTX_EN6:
case CS53L30_ASP_CTL2:
case CS53L30_SFT_RAMP:
case CS53L30_LRCK_CTL1:
case CS53L30_LRCK_CTL2:
case CS53L30_MUTEP_CTL1:
case CS53L30_MUTEP_CTL2:
case CS53L30_INBIAS_CTL1:
case CS53L30_INBIAS_CTL2:
case CS53L30_DMIC1_STR_CTL:
case CS53L30_DMIC2_STR_CTL:
case CS53L30_ADCDMIC1_CTL1:
case CS53L30_ADCDMIC1_CTL2:
case CS53L30_ADC1_CTL3:
case CS53L30_ADC1_NG_CTL:
case CS53L30_ADC1A_AFE_CTL:
case CS53L30_ADC1B_AFE_CTL:
case CS53L30_ADC1A_DIG_VOL:
case CS53L30_ADC1B_DIG_VOL:
case CS53L30_ADCDMIC2_CTL1:
case CS53L30_ADCDMIC2_CTL2:
case CS53L30_ADC2_CTL3:
case CS53L30_ADC2_NG_CTL:
case CS53L30_ADC2A_AFE_CTL:
case CS53L30_ADC2B_AFE_CTL:
case CS53L30_ADC2A_DIG_VOL:
case CS53L30_ADC2B_DIG_VOL:
case CS53L30_INT_MASK:
return true;
default:
return false;
}
}
static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2000, 0);
static DECLARE_TLV_DB_SCALE(adc_ng_boost_tlv, 0, 3000, 0);
static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
static DECLARE_TLV_DB_SCALE(dig_tlv, -9600, 100, 1);
static DECLARE_TLV_DB_SCALE(pga_preamp_tlv, 0, 10000, 0);
static const char * const input1_sel_text[] = {
"DMIC1 On AB In",
"DMIC1 On A In",
"DMIC1 On B In",
"ADC1 On AB In",
"ADC1 On A In",
"ADC1 On B In",
"DMIC1 Off ADC1 Off",
};
static unsigned int const input1_sel_values[] = {
CS53L30_CH_TYPE,
CS53L30_ADCxB_PDN | CS53L30_CH_TYPE,
CS53L30_ADCxA_PDN | CS53L30_CH_TYPE,
CS53L30_DMICx_PDN,
CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
};
static const char * const input2_sel_text[] = {
"DMIC2 On AB In",
"DMIC2 On A In",
"DMIC2 On B In",
"ADC2 On AB In",
"ADC2 On A In",
"ADC2 On B In",
"DMIC2 Off ADC2 Off",
};
static unsigned int const input2_sel_values[] = {
0x0,
CS53L30_ADCxB_PDN,
CS53L30_ADCxA_PDN,
CS53L30_DMICx_PDN,
CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
};
static const char * const input1_route_sel_text[] = {
"ADC1_SEL", "DMIC1_SEL",
};
static const struct soc_enum input1_route_sel_enum =
SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, CS53L30_CH_TYPE_SHIFT,
ARRAY_SIZE(input1_route_sel_text),
input1_route_sel_text);
static SOC_VALUE_ENUM_SINGLE_DECL(input1_sel_enum, CS53L30_ADCDMIC1_CTL1, 0,
CS53L30_ADCDMICx_PDN_MASK, input1_sel_text,
input1_sel_values);
static const struct snd_kcontrol_new input1_route_sel_mux =
SOC_DAPM_ENUM("Input 1 Route", input1_route_sel_enum);
static const char * const input2_route_sel_text[] = {
"ADC2_SEL", "DMIC2_SEL",
};
/* Note: CS53L30_ADCDMIC1_CTL1 CH_TYPE controls inputs 1 and 2 */
static const struct soc_enum input2_route_sel_enum =
SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0,
ARRAY_SIZE(input2_route_sel_text),
input2_route_sel_text);
static SOC_VALUE_ENUM_SINGLE_DECL(input2_sel_enum, CS53L30_ADCDMIC2_CTL1, 0,
CS53L30_ADCDMICx_PDN_MASK, input2_sel_text,
input2_sel_values);
static const struct snd_kcontrol_new input2_route_sel_mux =
SOC_DAPM_ENUM("Input 2 Route", input2_route_sel_enum);
/*
* TB = 6144*(MCLK(int) scaling factor)/MCLK(internal)
* TB - Time base
* NOTE: If MCLK_INT_SCALE = 0, then TB=1
*/
static const char * const cs53l30_ng_delay_text[] = {
"TB*50ms", "TB*100ms", "TB*150ms", "TB*200ms",
};
static const struct soc_enum adc1_ng_delay_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
ARRAY_SIZE(cs53l30_ng_delay_text),
cs53l30_ng_delay_text);
static const struct soc_enum adc2_ng_delay_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
ARRAY_SIZE(cs53l30_ng_delay_text),
cs53l30_ng_delay_text);
/* The noise gate threshold selected will depend on NG Boost */
static const char * const cs53l30_ng_thres_text[] = {
"-64dB/-34dB", "-66dB/-36dB", "-70dB/-40dB", "-73dB/-43dB",
"-76dB/-46dB", "-82dB/-52dB", "-58dB", "-64dB",
};
static const struct soc_enum adc1_ng_thres_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
ARRAY_SIZE(cs53l30_ng_thres_text),
cs53l30_ng_thres_text);
static const struct soc_enum adc2_ng_thres_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
ARRAY_SIZE(cs53l30_ng_thres_text),
cs53l30_ng_thres_text);
/* Corner frequencies are with an Fs of 48kHz. */
static const char * const hpf_corner_freq_text[] = {
"1.86Hz", "120Hz", "235Hz", "466Hz",
};
static const struct soc_enum adc1_hpf_enum =
SOC_ENUM_SINGLE(CS53L30_ADC1_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
static const struct soc_enum adc2_hpf_enum =
SOC_ENUM_SINGLE(CS53L30_ADC2_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
static const struct snd_kcontrol_new cs53l30_snd_controls[] = {
SOC_SINGLE("Digital Soft-Ramp Switch", CS53L30_SFT_RAMP,
CS53L30_DIGSFT_SHIFT, 1, 0),
SOC_SINGLE("ADC1 Noise Gate Ganging Switch", CS53L30_ADC1_CTL3,
CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
SOC_SINGLE("ADC2 Noise Gate Ganging Switch", CS53L30_ADC2_CTL3,
CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
SOC_SINGLE("ADC1A Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
CS53L30_ADCxA_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC1B Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
CS53L30_ADCxB_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC2A Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
CS53L30_ADCxA_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC2B Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
CS53L30_ADCxB_NG_SHIFT, 1, 0),
SOC_SINGLE("ADC1 Notch Filter Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
SOC_SINGLE("ADC2 Notch Filter Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
SOC_SINGLE("ADC1A Invert Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxA_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC1B Invert Switch", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxB_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC2A Invert Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxA_INV_SHIFT, 1, 0),
SOC_SINGLE("ADC2B Invert Switch", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxB_INV_SHIFT, 1, 0),
SOC_SINGLE_TLV("ADC1A Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC1B Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC2A Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC2B Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("ADC1 NG Boost Volume", CS53L30_ADC1_NG_CTL,
CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
SOC_SINGLE_TLV("ADC2 NG Boost Volume", CS53L30_ADC2_NG_CTL,
CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
SOC_DOUBLE_R_TLV("ADC1 Preamplifier Volume", CS53L30_ADC1A_AFE_CTL,
CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
2, 0, pga_preamp_tlv),
SOC_DOUBLE_R_TLV("ADC2 Preamplifier Volume", CS53L30_ADC2A_AFE_CTL,
CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
2, 0, pga_preamp_tlv),
SOC_ENUM("Input 1 Channel Select", input1_sel_enum),
SOC_ENUM("Input 2 Channel Select", input2_sel_enum),
SOC_ENUM("ADC1 HPF Select", adc1_hpf_enum),
SOC_ENUM("ADC2 HPF Select", adc2_hpf_enum),
SOC_ENUM("ADC1 NG Threshold", adc1_ng_thres_enum),
SOC_ENUM("ADC2 NG Threshold", adc2_ng_thres_enum),
SOC_ENUM("ADC1 NG Delay", adc1_ng_delay_enum),
SOC_ENUM("ADC2 NG Delay", adc2_ng_delay_enum),
SOC_SINGLE_SX_TLV("ADC1A PGA Volume",
CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
SOC_SINGLE_SX_TLV("ADC1B PGA Volume",
CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
SOC_SINGLE_SX_TLV("ADC2A PGA Volume",
CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
SOC_SINGLE_SX_TLV("ADC2B PGA Volume",
CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
SOC_SINGLE_SX_TLV("ADC1A Digital Volume",
CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC1B Digital Volume",
CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC2A Digital Volume",
CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
SOC_SINGLE_SX_TLV("ADC2B Digital Volume",
CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
};
static const struct snd_soc_dapm_widget cs53l30_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1_DMIC1"),
SND_SOC_DAPM_INPUT("IN2"),
SND_SOC_DAPM_INPUT("IN3_DMIC2"),
SND_SOC_DAPM_INPUT("IN4"),
SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC1_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC2_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC3 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC3_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIC4 Bias", CS53L30_MICBIAS_CTL,
CS53L30_MIC4_BIAS_PDN_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_AIF_OUT("ASP_SDOUT1", NULL, 0, CS53L30_ASP_CTL1,
CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
SND_SOC_DAPM_AIF_OUT("ASP_SDOUT2", NULL, 0, CS53L30_ASP_CTL2,
CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
SND_SOC_DAPM_MUX("Input Mux 1", SND_SOC_NOPM, 0, 0,
&input1_route_sel_mux),
SND_SOC_DAPM_MUX("Input Mux 2", SND_SOC_NOPM, 0, 0,
&input2_route_sel_mux),
SND_SOC_DAPM_ADC("ADC1A", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_ADCxA_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC1B", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_ADCxB_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC2A", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_ADCxA_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC2B", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_ADCxB_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("DMIC1", NULL, CS53L30_ADCDMIC1_CTL1,
CS53L30_DMICx_PDN_SHIFT, 1),
SND_SOC_DAPM_ADC("DMIC2", NULL, CS53L30_ADCDMIC2_CTL1,
CS53L30_DMICx_PDN_SHIFT, 1),
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes[] = {
/* ADC Input Paths */
{"ADC1A", NULL, "IN1_DMIC1"},
{"Input Mux 1", "ADC1_SEL", "ADC1A"},
{"ADC1B", NULL, "IN2"},
{"ADC2A", NULL, "IN3_DMIC2"},
{"Input Mux 2", "ADC2_SEL", "ADC2A"},
{"ADC2B", NULL, "IN4"},
/* MIC Bias Paths */
{"ADC1A", NULL, "MIC1 Bias"},
{"ADC1B", NULL, "MIC2 Bias"},
{"ADC2A", NULL, "MIC3 Bias"},
{"ADC2B", NULL, "MIC4 Bias"},
/* DMIC Paths */
{"DMIC1", NULL, "IN1_DMIC1"},
{"Input Mux 1", "DMIC1_SEL", "DMIC1"},
{"DMIC2", NULL, "IN3_DMIC2"},
{"Input Mux 2", "DMIC2_SEL", "DMIC2"},
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout1[] = {
/* Output Paths when using SDOUT1 only */
{"ASP_SDOUT1", NULL, "ADC1A" },
{"ASP_SDOUT1", NULL, "Input Mux 1"},
{"ASP_SDOUT1", NULL, "ADC1B"},
{"ASP_SDOUT1", NULL, "ADC2A"},
{"ASP_SDOUT1", NULL, "Input Mux 2"},
{"ASP_SDOUT1", NULL, "ADC2B"},
{"Capture", NULL, "ASP_SDOUT1"},
};
static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout2[] = {
/* Output Paths when using both SDOUT1 and SDOUT2 */
{"ASP_SDOUT1", NULL, "ADC1A" },
{"ASP_SDOUT1", NULL, "Input Mux 1"},
{"ASP_SDOUT1", NULL, "ADC1B"},
{"ASP_SDOUT2", NULL, "ADC2A"},
{"ASP_SDOUT2", NULL, "Input Mux 2"},
{"ASP_SDOUT2", NULL, "ADC2B"},
{"Capture", NULL, "ASP_SDOUT1"},
{"Capture", NULL, "ASP_SDOUT2"},
};
struct cs53l30_mclk_div {
u32 mclk_rate;
u32 srate;
u8 asp_rate;
u8 internal_fs_ratio;
u8 mclk_int_scale;
};
static const struct cs53l30_mclk_div cs53l30_mclk_coeffs[] = {
/* NOTE: Enable MCLK_INT_SCALE to save power. */
/* MCLK, Sample Rate, asp_rate, internal_fs_ratio, mclk_int_scale */
{5644800, 11025, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{5644800, 22050, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{5644800, 44100, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6000000, 8000, 0x1, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 11025, 0x2, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 12000, 0x4, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 16000, 0x5, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 22050, 0x6, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 24000, 0x8, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 32000, 0x9, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 44100, 0xA, 0, CS53L30_MCLK_INT_SCALE},
{6000000, 48000, 0xC, 0, CS53L30_MCLK_INT_SCALE},
{6144000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6144000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
{6400000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
};
struct cs53l30_mclkx_div {
u32 mclkx;
u8 ratio;
u8 mclkdiv;
};
static const struct cs53l30_mclkx_div cs53l30_mclkx_coeffs[] = {
{5644800, 1, CS53L30_MCLK_DIV_BY_1},
{6000000, 1, CS53L30_MCLK_DIV_BY_1},
{6144000, 1, CS53L30_MCLK_DIV_BY_1},
{11289600, 2, CS53L30_MCLK_DIV_BY_2},
{12288000, 2, CS53L30_MCLK_DIV_BY_2},
{12000000, 2, CS53L30_MCLK_DIV_BY_2},
{19200000, 3, CS53L30_MCLK_DIV_BY_3},
};
static int cs53l30_get_mclkx_coeff(int mclkx)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs53l30_mclkx_coeffs); i++) {
if (cs53l30_mclkx_coeffs[i].mclkx == mclkx)
return i;
}
return -EINVAL;
}
static int cs53l30_get_mclk_coeff(int mclk_rate, int srate)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs53l30_mclk_coeffs); i++) {
if (cs53l30_mclk_coeffs[i].mclk_rate == mclk_rate &&
cs53l30_mclk_coeffs[i].srate == srate)
return i;
}
return -EINVAL;
}
static int cs53l30_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
int mclkx_coeff;
u32 mclk_rate;
/* MCLKX -> MCLK */
mclkx_coeff = cs53l30_get_mclkx_coeff(freq);
if (mclkx_coeff < 0)
return mclkx_coeff;
mclk_rate = cs53l30_mclkx_coeffs[mclkx_coeff].mclkx /
cs53l30_mclkx_coeffs[mclkx_coeff].ratio;
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIV_MASK,
cs53l30_mclkx_coeffs[mclkx_coeff].mclkdiv);
priv->mclk_rate = mclk_rate;
return 0;
}
static int cs53l30_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
u8 aspcfg = 0, aspctl1 = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
aspcfg |= CS53L30_ASP_MS;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* DAI mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* Set TDM_PDN to turn off TDM mode -- Reset default */
aspctl1 |= CS53L30_ASP_TDM_PDN;
break;
case SND_SOC_DAIFMT_DSP_A:
/*
* Clear TDM_PDN to turn on TDM mode; Use ASP_SCLK_INV = 0
* with SHIFT_LEFT = 1 combination as Figure 4-13 shows in
* the CS53L30 datasheet
*/
aspctl1 |= CS53L30_SHIFT_LEFT;
break;
default:
return -EINVAL;
}
/* Check to see if the SCLK is inverted */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_NF:
case SND_SOC_DAIFMT_IB_IF:
aspcfg ^= CS53L30_ASP_SCLK_INV;
break;
default:
break;
}
regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
CS53L30_ASP_MS | CS53L30_ASP_SCLK_INV, aspcfg);
regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
CS53L30_ASP_TDM_PDN | CS53L30_SHIFT_LEFT, aspctl1);
return 0;
}
static int cs53l30_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
int srate = params_rate(params);
int mclk_coeff;
/* MCLK -> srate */
mclk_coeff = cs53l30_get_mclk_coeff(priv->mclk_rate, srate);
if (mclk_coeff < 0)
return -EINVAL;
regmap_update_bits(priv->regmap, CS53L30_INT_SR_CTL,
CS53L30_INTRNL_FS_RATIO_MASK,
cs53l30_mclk_coeffs[mclk_coeff].internal_fs_ratio);
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_INT_SCALE_MASK,
cs53l30_mclk_coeffs[mclk_coeff].mclk_int_scale);
regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
CS53L30_ASP_RATE_MASK,
cs53l30_mclk_coeffs[mclk_coeff].asp_rate);
return 0;
}
static int cs53l30_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec);
unsigned int reg;
int i, inter_max_check, ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
if (dapm->bias_level == SND_SOC_BIAS_STANDBY)
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_LP_MASK, 0);
break;
case SND_SOC_BIAS_STANDBY:
if (dapm->bias_level == SND_SOC_BIAS_OFF) {
ret = clk_prepare_enable(priv->mclk);
if (ret) {
dev_err(codec->dev,
"failed to enable MCLK: %d\n", ret);
return ret;
}
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIS_MASK, 0);
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK, 0);
msleep(50);
} else {
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK,
CS53L30_PDN_ULP);
}
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
CS53L30_PDN_DONE, 0);
/*
* If digital softramp is set, the amount of time required
* for power down increases and depends on the digital
* volume setting.
*/
/* Set the max possible time if digsft is set */
regmap_read(priv->regmap, CS53L30_SFT_RAMP, &reg);
if (reg & CS53L30_DIGSFT_MASK)
inter_max_check = CS53L30_PDN_POLL_MAX;
else
inter_max_check = 10;
regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
CS53L30_PDN_ULP_MASK,
CS53L30_PDN_ULP);
/* PDN_DONE will take a min of 20ms to be set.*/
msleep(20);
/* Clr status */
regmap_read(priv->regmap, CS53L30_IS, &reg);
for (i = 0; i < inter_max_check; i++) {
if (inter_max_check < 10) {
usleep_range(1000, 1100);
regmap_read(priv->regmap, CS53L30_IS, &reg);
if (reg & CS53L30_PDN_DONE)
break;
} else {
usleep_range(10000, 10100);
regmap_read(priv->regmap, CS53L30_IS, &reg);
if (reg & CS53L30_PDN_DONE)
break;
}
}
/* PDN_DONE is set. We now can disable the MCLK */
regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
CS53L30_PDN_DONE, CS53L30_PDN_DONE);
regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
CS53L30_MCLK_DIS_MASK,
CS53L30_MCLK_DIS);
clk_disable_unprepare(priv->mclk);
break;
}
return 0;
}
static int cs53l30_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
u8 val = tristate ? CS53L30_ASP_3ST : 0;
return regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
CS53L30_ASP_3ST_MASK, val);
}
static unsigned int const cs53l30_src_rates[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
};
static struct snd_pcm_hw_constraint_list src_constraints = {
.count = ARRAY_SIZE(cs53l30_src_rates),
.list = cs53l30_src_rates,
};
static int cs53l30_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &src_constraints);
return 0;
}
/*
* Note: CS53L30 counts the slot number per byte while ASoC counts the slot
* number per slot_width. So there is a difference between the slots of ASoC
* and the slots of CS53L30.
*/
static int cs53l30_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
unsigned int loc[CS53L30_TDM_SLOT_MAX] = {48, 48, 48, 48};
unsigned int slot_next, slot_step;
u64 tx_enable = 0;
int i;
if (!rx_mask) {
dev_err(dai->dev, "rx masks must not be 0\n");
return -EINVAL;
}
/* Assuming slot_width is not supposed to be greater than 64 */
if (slots <= 0 || slot_width <= 0 || slot_width > 64) {
dev_err(dai->dev, "invalid slot number or slot width\n");
return -EINVAL;
}
if (slot_width & 0x7) {
dev_err(dai->dev, "slot width must count in byte\n");
return -EINVAL;
}
/* How many bytes in each ASoC slot */
slot_step = slot_width >> 3;
for (i = 0; rx_mask && i < CS53L30_TDM_SLOT_MAX; i++) {
/* Find the first slot from LSB */
slot_next = __ffs(rx_mask);
/* Save the slot location by converting to CS53L30 slot */
loc[i] = slot_next * slot_step;
/* Create the mask of CS53L30 slot */
tx_enable |= (u64)((u64)(1 << slot_step) - 1) << (u64)loc[i];
/* Clear this slot from rx_mask */
rx_mask &= ~(1 << slot_next);
}
/* Error out to avoid slot shift */
if (rx_mask && i == CS53L30_TDM_SLOT_MAX) {
dev_err(dai->dev, "rx_mask exceeds max slot number: %d\n",
CS53L30_TDM_SLOT_MAX);
return -EINVAL;
}
/* Validate the last active CS53L30 slot */
slot_next = loc[i - 1] + slot_step - 1;
if (slot_next > 47) {
dev_err(dai->dev, "slot selection out of bounds: %u\n",
slot_next);
return -EINVAL;
}
for (i = 0; i < CS53L30_TDM_SLOT_MAX && loc[i] != 48; i++) {
regmap_update_bits(priv->regmap, CS53L30_ASP_TDMTX_CTL(i),
CS53L30_ASP_CHx_TX_LOC_MASK, loc[i]);
dev_dbg(dai->dev, "loc[%d]=%x\n", i, loc[i]);
}
for (i = 0; i < CS53L30_ASP_TDMTX_ENx_MAX && tx_enable; i++) {
regmap_write(priv->regmap, CS53L30_ASP_TDMTX_ENx(i),
tx_enable & 0xff);
tx_enable >>= 8;
dev_dbg(dai->dev, "en_reg=%x, tx_enable=%llx\n",
CS53L30_ASP_TDMTX_ENx(i), tx_enable & 0xff);
}
return 0;
}
static int cs53l30_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
if (priv->mute_gpio)
gpiod_set_value_cansleep(priv->mute_gpio, mute);
return 0;
}
/* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */
#define CS53L30_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT)
#define CS53L30_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops cs53l30_ops = {
.startup = cs53l30_pcm_startup,
.hw_params = cs53l30_pcm_hw_params,
.set_fmt = cs53l30_set_dai_fmt,
.set_sysclk = cs53l30_set_sysclk,
.set_tristate = cs53l30_set_tristate,
.set_tdm_slot = cs53l30_set_dai_tdm_slot,
.mute_stream = cs53l30_mute_stream,
};
static struct snd_soc_dai_driver cs53l30_dai = {
.name = "cs53l30",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = CS53L30_RATES,
.formats = CS53L30_FORMATS,
},
.ops = &cs53l30_ops,
.symmetric_rates = 1,
};
static int cs53l30_codec_probe(struct snd_soc_codec *codec)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(codec);
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
if (priv->use_sdout2)
snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout2,
ARRAY_SIZE(cs53l30_dapm_routes_sdout2));
else
snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout1,
ARRAY_SIZE(cs53l30_dapm_routes_sdout1));
return 0;
}
static struct snd_soc_codec_driver cs53l30_driver = {
.probe = cs53l30_codec_probe,
.set_bias_level = cs53l30_set_bias_level,
.idle_bias_off = true,
.component_driver = {
.controls = cs53l30_snd_controls,
.num_controls = ARRAY_SIZE(cs53l30_snd_controls),
.dapm_widgets = cs53l30_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs53l30_dapm_widgets),
.dapm_routes = cs53l30_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs53l30_dapm_routes),
},
};
static struct regmap_config cs53l30_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS53L30_MAX_REGISTER,
.reg_defaults = cs53l30_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs53l30_reg_defaults),
.volatile_reg = cs53l30_volatile_register,
.writeable_reg = cs53l30_writeable_register,
.readable_reg = cs53l30_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static int cs53l30_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
const struct device_node *np = client->dev.of_node;
struct device *dev = &client->dev;
struct cs53l30_private *cs53l30;
unsigned int devid = 0;
unsigned int reg;
int ret = 0, i;
u8 val;
cs53l30 = devm_kzalloc(dev, sizeof(*cs53l30), GFP_KERNEL);
if (!cs53l30)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(cs53l30->supplies); i++)
cs53l30->supplies[i].supply = cs53l30_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to get supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
return ret;
}
/* Reset the Device */
cs53l30->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs53l30->reset_gpio)) {
ret = PTR_ERR(cs53l30->reset_gpio);
goto error;
}
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
i2c_set_clientdata(client, cs53l30);
cs53l30->mclk_rate = 0;
cs53l30->regmap = devm_regmap_init_i2c(client, &cs53l30_regmap);
if (IS_ERR(cs53l30->regmap)) {
ret = PTR_ERR(cs53l30->regmap);
dev_err(dev, "regmap_init() failed: %d\n", ret);
goto error;
}
/* Initialize codec */
ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_AB, &reg);
devid = reg << 12;
ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_CD, &reg);
devid |= reg << 4;
ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_E, &reg);
devid |= (reg & 0xF0) >> 4;
if (devid != CS53L30_DEVID) {
ret = -ENODEV;
dev_err(dev, "Device ID (%X). Expected %X\n",
devid, CS53L30_DEVID);
goto error;
}
ret = regmap_read(cs53l30->regmap, CS53L30_REVID, &reg);
if (ret < 0) {
dev_err(dev, "failed to get Revision ID: %d\n", ret);
goto error;
}
/* Check if MCLK provided */
cs53l30->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(cs53l30->mclk)) {
if (PTR_ERR(cs53l30->mclk) != -ENOENT) {
ret = PTR_ERR(cs53l30->mclk);
goto error;
}
/* Otherwise mark the mclk pointer to NULL */
cs53l30->mclk = NULL;
}
/* Fetch the MUTE control */
cs53l30->mute_gpio = devm_gpiod_get_optional(dev, "mute",
GPIOD_OUT_HIGH);
if (IS_ERR(cs53l30->mute_gpio)) {
ret = PTR_ERR(cs53l30->mute_gpio);
goto error;
}
if (cs53l30->mute_gpio) {
/* Enable MUTE controls via MUTE pin */
regmap_write(cs53l30->regmap, CS53L30_MUTEP_CTL1,
CS53L30_MUTEP_CTL1_MUTEALL);
/* Flip the polarity of MUTE pin */
if (gpiod_is_active_low(cs53l30->mute_gpio))
regmap_update_bits(cs53l30->regmap, CS53L30_MUTEP_CTL2,
CS53L30_MUTE_PIN_POLARITY, 0);
}
if (!of_property_read_u8(np, "cirrus,micbias-lvl", &val))
regmap_update_bits(cs53l30->regmap, CS53L30_MICBIAS_CTL,
CS53L30_MIC_BIAS_CTRL_MASK, val);
if (of_property_read_bool(np, "cirrus,use-sdout2"))
cs53l30->use_sdout2 = true;
dev_info(dev, "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF);
ret = snd_soc_register_codec(dev, &cs53l30_driver, &cs53l30_dai, 1);
if (ret) {
dev_err(dev, "failed to register codec: %d\n", ret);
goto error;
}
return 0;
error:
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
return ret;
}
static int cs53l30_i2c_remove(struct i2c_client *client)
{
struct cs53l30_private *cs53l30 = i2c_get_clientdata(client);
snd_soc_unregister_codec(&client->dev);
/* Hold down reset */
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
return 0;
}
#ifdef CONFIG_PM
static int cs53l30_runtime_suspend(struct device *dev)
{
struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
regcache_cache_only(cs53l30->regmap, true);
/* Hold down reset */
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
return 0;
}
static int cs53l30_runtime_resume(struct device *dev)
{
struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
if (ret) {
dev_err(dev, "failed to enable supplies: %d\n", ret);
return ret;
}
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
regcache_cache_only(cs53l30->regmap, false);
ret = regcache_sync(cs53l30->regmap);
if (ret) {
dev_err(dev, "failed to synchronize regcache: %d\n", ret);
return ret;
}
return 0;
}
#endif
static const struct dev_pm_ops cs53l30_runtime_pm = {
SET_RUNTIME_PM_OPS(cs53l30_runtime_suspend, cs53l30_runtime_resume,
NULL)
};
static const struct of_device_id cs53l30_of_match[] = {
{ .compatible = "cirrus,cs53l30", },
{},
};
MODULE_DEVICE_TABLE(of, cs53l30_of_match);
static const struct i2c_device_id cs53l30_id[] = {
{ "cs53l30", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, cs53l30_id);
static struct i2c_driver cs53l30_i2c_driver = {
.driver = {
.name = "cs53l30",
.pm = &cs53l30_runtime_pm,
},
.id_table = cs53l30_id,
.probe = cs53l30_i2c_probe,
.remove = cs53l30_i2c_remove,
};
module_i2c_driver(cs53l30_i2c_driver);
MODULE_DESCRIPTION("ASoC CS53L30 driver");
MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>");
MODULE_LICENSE("GPL");
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