714 lines
17 KiB
C
714 lines
17 KiB
C
/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Chen Zhong <chen.zhong@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include "clkdbg.h"
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#define DUMP_INIT_STATE 0
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/*
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* clkdbg dump_regs
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*/
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enum {
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infrasys,
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perisys,
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scpsys,
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apmixed,
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fhctl,
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topckgen,
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audio,
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ssusb,
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pcie,
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ethdma,
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sgmii,
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};
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#define REGBASE_V(_phys, _id_name) { .phys = _phys, .name = #_id_name }
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/*
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* checkpatch.pl ERROR:COMPLEX_MACRO
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*
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* #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
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*/
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static struct regbase rb[] = {
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[infrasys] = REGBASE_V(0x10000000, infrasys),
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[perisys] = REGBASE_V(0x10002000, perisys),
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[scpsys] = REGBASE_V(0x10006000, scpsys),
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[apmixed] = REGBASE_V(0x10209000, apmixed),
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[fhctl] = REGBASE_V(0x10209f00, fhctl),
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[topckgen] = REGBASE_V(0x10210000, topckgen),
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[audio] = REGBASE_V(0x11220000, audio),
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[ssusb] = REGBASE_V(0x1A000000, ssusb),
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[pcie] = REGBASE_V(0x1A100800, pcie),
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[ethdma] = REGBASE_V(0x1B000000, ethdma),
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[sgmii] = REGBASE_V(0x1B128000, sgmii),
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};
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#define REGNAME(_base, _ofs, _name) \
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{ .base = &rb[_base], .ofs = _ofs, .name = #_name }
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static struct regname rn[] = {
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REGNAME(infrasys, 0x040, INFRA_GLOBALCON_PDN0),
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REGNAME(infrasys, 0x044, INFRA_GLOBALCON_PDN1),
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REGNAME(infrasys, 0x048, INFRA_PDN_STA),
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REGNAME(perisys, 0x008, PERI_GLOBALCON_PDN0_SET),
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REGNAME(perisys, 0x00C, PERI_GLOBALCON_PDN1_SET),
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REGNAME(perisys, 0x010, PERI_GLOBALCON_PDN0_CLR),
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REGNAME(perisys, 0x014, PERI_GLOBALCON_PDN1_CLR),
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REGNAME(perisys, 0x018, PERI_GLOBALCON_PDN0_STA),
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REGNAME(perisys, 0x01C, PERI_GLOBALCON_PDN1_STA),
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REGNAME(scpsys, 0x2E0, SPM_ETH_PWR_CON),
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REGNAME(scpsys, 0x2E4, SPM_HIF0_PWR_CON),
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REGNAME(scpsys, 0x2E8, SPM_HIF1_PWR_CON),
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REGNAME(scpsys, 0x60c, SPM_PWR_STATUS),
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REGNAME(scpsys, 0x610, SPM_PWR_STATUS_2ND),
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REGNAME(apmixed, 0x200, ARMPLL_CON0),
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REGNAME(apmixed, 0x204, ARMPLL_CON1),
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REGNAME(apmixed, 0x20C, ARMPLL_PWR_CON0),
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REGNAME(apmixed, 0x210, MAINPLL_CON0),
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REGNAME(apmixed, 0x214, MAINPLL_CON1),
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REGNAME(apmixed, 0x21C, MAINPLL_PWR_CON0),
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REGNAME(apmixed, 0x220, UNIVPLL_CON0),
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REGNAME(apmixed, 0x224, UNIVPLL_CON1),
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REGNAME(apmixed, 0x22C, UNIVPLL_PWR_CON0),
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REGNAME(apmixed, 0x300, ETH1PLL_CON0),
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REGNAME(apmixed, 0x304, ETH1PLL_CON1),
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REGNAME(apmixed, 0x310, ETH1PLL_PWR_CON0),
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REGNAME(apmixed, 0x314, ETH2PLL_CON0),
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REGNAME(apmixed, 0x318, ETH2PLL_CON1),
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REGNAME(apmixed, 0x320, ETH2PLL_PWR_CON0),
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REGNAME(apmixed, 0x324, APLL1_CON0),
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REGNAME(apmixed, 0x328, APLL1_CON1),
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REGNAME(apmixed, 0x330, APLL1_PWR_CON0),
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REGNAME(apmixed, 0x334, APLL2_CON0),
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REGNAME(apmixed, 0x338, APLL2_CON1),
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REGNAME(apmixed, 0x340, APLL2_PWR_CON0),
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REGNAME(apmixed, 0x344, TRGPLL_CON0),
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REGNAME(apmixed, 0x348, TRGPLL_CON1),
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REGNAME(apmixed, 0x354, TRGPLL_PWR_CON0),
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REGNAME(apmixed, 0x358, SGMIPLL_CON0),
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REGNAME(apmixed, 0x35C, SGMIPLL_CON1),
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REGNAME(apmixed, 0x368, SGMIPLL_PWR_CON0),
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REGNAME(topckgen, 0x040, CLK_CFG_0),
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REGNAME(topckgen, 0x050, CLK_CFG_1),
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REGNAME(topckgen, 0x060, CLK_CFG_2),
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REGNAME(topckgen, 0x070, CLK_CFG_3),
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REGNAME(topckgen, 0x080, CLK_CFG_4),
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REGNAME(topckgen, 0x090, CLK_CFG_5),
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REGNAME(topckgen, 0x0A0, CLK_CFG_6),
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REGNAME(topckgen, 0x0B0, CLK_CFG_7),
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REGNAME(topckgen, 0x120, CLK_AUDDIV_0),
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REGNAME(topckgen, 0x128, CLK_AUDDIV_2),
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REGNAME(audio, 0x000, AUDIO_TOP_CON0),
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REGNAME(audio, 0x010, AUDIO_TOP_CON4),
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REGNAME(audio, 0x014, AUDIO_TOP_CON5),
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REGNAME(audio, 0x634, PWR2_TOP_CON),
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REGNAME(ssusb, 0x30, USB23_CSR_O_CLKCFG1),
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REGNAME(pcie, 0x30, COMBO_CSR_O_CLKCFG1),
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REGNAME(ethdma, 0x30, ETHDMACTL_CLKCFG1),
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REGNAME(sgmii, 0xE4, SGMII_QPHY_CTRL),
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{NULL, 0, NULL}
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};
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static const struct regname *get_all_regnames(void)
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{
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return rn;
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}
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static void __init init_regbase(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(rb); i++)
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rb[i].virt = ioremap(rb[i].phys, PAGE_SIZE);
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}
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/*
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* clkdbg fmeter
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*/
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#include <linux/delay.h>
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#ifndef GENMASK
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#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
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#endif
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#define ALT_BITS(o, h, l, v) \
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(((o) & ~GENMASK(h, l)) | (((v) << (l)) & GENMASK(h, l)))
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#define clk_readl(addr) readl(addr)
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#define clk_writel(addr, val) \
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do { writel(val, addr); wmb(); } while (0) /* sync write */
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#define clk_writel_mask(addr, mask, val) \
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clk_writel(addr, (clk_readl(addr) & ~(mask)) | (val))
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#define ABS_DIFF(a, b) ((a) > (b) ? (a) - (b) : (b) - (a))
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enum FMETER_TYPE {
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FT_NULL,
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ABIST,
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CKGEN
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};
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#define FMCLK(_t, _i, _n) { .type = _t, .id = _i, .name = _n }
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static const struct fmeter_clk fclks[] = {
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FMCLK(ABIST, 1, "AD_MEMPLL2_CKOUT0_PRE_ISO"),
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FMCLK(ABIST, 2, "AD_MAIN_DIV2_CK"),
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FMCLK(ABIST, 3, "AD_MAIN_DIV3_CK"),
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FMCLK(ABIST, 4, "AD_MAIN_DIV5_CK"),
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FMCLK(ABIST, 5, "AD_MAIN_DIV7_CK"),
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FMCLK(ABIST, 6, "AD_UNIV_DIV2_CK"),
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FMCLK(ABIST, 7, "AD_UNIV_DIV3_CK"),
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FMCLK(ABIST, 8, "AD_UNIV_DIV5_CK"),
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FMCLK(ABIST, 9, "AD_UNIV_DIV7_CK"),
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FMCLK(ABIST, 10, "AD_UNIV_DIV80_CK"),
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FMCLK(ABIST, 11, "AD_UNIV_48M_CK"),
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FMCLK(ABIST, 12, "AD_SGMIIPLL_CK"),
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FMCLK(ABIST, 13, "XTAL"),
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FMCLK(ABIST, 14, "AD_AUD1PLL_CK"),
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FMCLK(ABIST, 15, "AD_AUD2PLL_CK"),
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FMCLK(ABIST, 16, "RTC"),
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FMCLK(ABIST, 17, "AD_ARMPLL_TOP_TST_CK"),
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FMCLK(ABIST, 18, "AD_USB_48M_CK"),
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FMCLK(ABIST, 19, "AD_MAINPLL_CORE_CK"),
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FMCLK(ABIST, 20, "AD_TRGPLL_CK"),
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FMCLK(ABIST, 21, "AD_MEM_25M_CK"),
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FMCLK(ABIST, 22, "AD_PLLGP_TST_CK"),
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FMCLK(ABIST, 23, "AD_ETH1PLL_CK"),
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FMCLK(ABIST, 24, "AD_ETH2PLL_CK"),
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FMCLK(ABIST, 25, "AD_UNIVPLL_CK"),
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FMCLK(ABIST, 26, "AD_MEM2MIPI_26M_CK"),
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FMCLK(ABIST, 27, "AD_MEMPLL_MONCLK"),
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FMCLK(ABIST, 28, "AD_MEMPLL2_MONCLK"),
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FMCLK(ABIST, 29, "AD_MEMPLL3_MONCLK"),
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FMCLK(ABIST, 30, "AD_MEMPLL4_MONCLK"),
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FMCLK(ABIST, 31, "AD_MEMPLL_REFCLK_BUF"),
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FMCLK(ABIST, 32, "AD_MEMPLL_FBCLK_BUF"),
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FMCLK(ABIST, 33, "AD_MEMPLL2_REFCLK_BUF"),
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FMCLK(ABIST, 34, "AD_MEMPLL2_FBCLK_BUF"),
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FMCLK(ABIST, 35, "AD_MEMPLL3_REFCLK_BUF"),
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FMCLK(ABIST, 36, "AD_MEMPLL3_FBCLK_BUF"),
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FMCLK(ABIST, 37, "AD_MEMPLL4_REFCLK_BUF"),
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FMCLK(ABIST, 38, "AD_MEMPLL4_FBCLK_BUF"),
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FMCLK(ABIST, 39, "AD_MEMPLL_TSTDIV2_CK"),
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FMCLK(CKGEN, 1, "hf_fmem_ck"),
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FMCLK(CKGEN, 2, "hf_fddrphycfg_ck"),
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FMCLK(CKGEN, 3, "hf_feth_ck"),
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FMCLK(CKGEN, 4, "f_fpwm_ck"),
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FMCLK(CKGEN, 5, "hf_f10m_ck"),
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FMCLK(CKGEN, 6, "hf_fspinfi_infra_bclk_ck"),
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FMCLK(CKGEN, 7, "hf_fflash_ck"),
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FMCLK(CKGEN, 8, "f_fuart_ck"),
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FMCLK(CKGEN, 9, "hf_fspi0_ck"),
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FMCLK(CKGEN, 10, "hf_fspi1_ck"),
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FMCLK(CKGEN, 11, "hf_fmsdc50_0_ck"),
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FMCLK(CKGEN, 12, "hf_fmsdc30_0_ck"),
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FMCLK(CKGEN, 13, "hf_fmsdc30_1_ck"),
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FMCLK(CKGEN, 14, "f_fa1sys_hp_ck"),
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FMCLK(CKGEN, 15, "f_fa2sys_hp_ck"),
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FMCLK(CKGEN, 16, "hf_fintdir_ck"),
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FMCLK(CKGEN, 17, "hf_faud_intbus_ck"),
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FMCLK(CKGEN, 18, "hf_fpmicspi_ck"),
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FMCLK(CKGEN, 19, "hf_fscp_ck"),
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FMCLK(CKGEN, 20, "hf_fatb_ck"),
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FMCLK(CKGEN, 21, "hf_fhif_ck"),
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FMCLK(CKGEN, 22, "hf_faudio_ck"),
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FMCLK(CKGEN, 23, "hf_fusb20_ck"),
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FMCLK(CKGEN, 24, "f_faud1_ck"),
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FMCLK(CKGEN, 25, "f_faud2_ck"),
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FMCLK(CKGEN, 26, "hf_firrx_ck"),
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FMCLK(CKGEN, 27, "hf_firtx_ck"),
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FMCLK(CKGEN, 28, "hf_fasm_l_ck"),
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FMCLK(CKGEN, 29, "hf_fasm_m_ck"),
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FMCLK(CKGEN, 30, "hf_fasm_h_ck"),
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FMCLK(CKGEN, 31, "f_faud26m_ck"),
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FMCLK(CKGEN, 32, "hf_fpmicspi_ck_scan"),
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FMCLK(CKGEN, 33, "hf_fsgmii_ref_ck"),
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FMCLK(CKGEN, 34, "f_fsata_ck"),
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FMCLK(CKGEN, 35, "f_f75k_ck"),
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FMCLK(CKGEN, 36, "f_fmsdc_ext_ck"),
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FMCLK(CKGEN, 37, "hf_fddrphycfg_ck_scan"),
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FMCLK(CKGEN, 38, "f_frtc_fddrphyperi_ck"),
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FMCLK(CKGEN, 39, "f_fddrphyperi_ck_scan"),
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FMCLK(CKGEN, 40, "f_fckrtc_ck_scan"),
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FMCLK(CKGEN, 41, "f_frtc_ck"),
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FMCLK(CKGEN, 42, "f_fxtal_ck"),
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FMCLK(CKGEN, 43, "f_fckbus_ck_scan"),
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FMCLK(CKGEN, 44, "f_fxtal_ck_cg"),
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FMCLK(CKGEN, 45, "hd_qaxidcm_ck"),
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FMCLK(CKGEN, 46, "hf_fspi0_pad_ck"),
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FMCLK(CKGEN, 47, "hf_fspi1_pad_ck"),
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FMCLK(CKGEN, 48, "f_fefuse_ck"),
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FMCLK(CKGEN, 49, "f_fapmixed_ck"),
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FMCLK(CKGEN, 50, "f_fclkmux_ck"),
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FMCLK(CKGEN, 51, "f_frtc_apmixed_ck"),
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FMCLK(CKGEN, 52, "f_fsata_ref_ck"),
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FMCLK(CKGEN, 53, "f_fpcie_ref_ck"),
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FMCLK(CKGEN, 54, "f_fssusb_ref_ck"),
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FMCLK(CKGEN, 55, "f_funivpll3_d16_ck"),
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FMCLK(CKGEN, 56, "f_fauxadc_ck"),
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FMCLK(CKGEN, 57, "hf_fap2wbmcu_ck"),
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FMCLK(CKGEN, 58, "hf_fap2wbhif_ck"),
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FMCLK(CKGEN, 59, "hf_fsata_mcu_ck"),
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FMCLK(CKGEN, 60, "hf_fpcie0_mcu_ck"),
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FMCLK(CKGEN, 61, "hf_fpcie1_mcu_ck"),
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FMCLK(CKGEN, 62, "hf_fssusb_mcu_ck"),
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FMCLK(CKGEN, 63, "f_fpcie_2ln_ck"),
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{}
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};
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#define FHCTL_HP_EN (rb[fhctl].virt + 0x000)
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#define CLK_CFG_M0 (rb[topckgen].virt + 0x100)
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#define CLK_CFG_M1 (rb[topckgen].virt + 0x104)
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#define CLK_MISC_CFG_1 (rb[topckgen].virt + 0x214)
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#define CLK_MISC_CFG_2 (rb[topckgen].virt + 0x218)
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#define CLK26CALI_0 (rb[topckgen].virt + 0x220)
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#define CLK26CALI_1 (rb[topckgen].virt + 0x224)
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#define CLK26CALI_2 (rb[topckgen].virt + 0x228)
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#define RG_FRMTR_WINDOW 1023
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static void set_fmeter_divider_arm(u32 k1)
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{
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u32 v = clk_readl(CLK_MISC_CFG_1);
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v = ALT_BITS(v, 15, 8, k1);
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clk_writel(CLK_MISC_CFG_1, v);
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}
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static void set_fmeter_divider(u32 k1)
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{
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u32 v = clk_readl(CLK_MISC_CFG_1);
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v = ALT_BITS(v, 7, 0, k1);
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v = ALT_BITS(v, 31, 24, k1);
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clk_writel(CLK_MISC_CFG_1, v);
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}
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static u8 wait_fmeter_done(u32 tri_bit)
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{
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static int max_wait_count;
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int wait_count = (max_wait_count > 0) ? (max_wait_count * 2 + 2) : 100;
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int i;
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/* wait fmeter */
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for (i = 0; i < wait_count && (clk_readl(CLK26CALI_0) & tri_bit); i++)
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udelay(20);
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if (!(clk_readl(CLK26CALI_0) & tri_bit)) {
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max_wait_count = max(max_wait_count, i);
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return 1;
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}
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return 0;
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}
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static u32 fmeter_freq(enum FMETER_TYPE type, int k1, int clk)
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{
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void __iomem *clk_cfg_reg = (type == CKGEN) ? CLK_CFG_M1 : CLK_CFG_M0;
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void __iomem *cnt_reg = (type == CKGEN) ? CLK26CALI_2 : CLK26CALI_1;
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u32 cksw_mask = (type == CKGEN) ? GENMASK(21, 16) : GENMASK(13, 8);
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u32 cksw_val = (type == CKGEN) ? (clk << 16) : (clk << 8);
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u32 tri_bit = (type == CKGEN) ? BIT(4) : BIT(0);
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u32 clk_exc = (type == CKGEN) ? BIT(5) : BIT(2);
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u32 clk_misc_cfg_1, clk_misc_cfg_2, clk_cfg_val, cnt, freq = 0;
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/* setup fmeter */
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clk_setl(CLK26CALI_0, BIT(7)); /* enable fmeter_en */
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clk_clrl(CLK26CALI_0, clk_exc); /* set clk_exc */
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clk_writel_mask(cnt_reg, GENMASK(25, 16), RG_FRMTR_WINDOW << 16); /* load_cnt */
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clk_misc_cfg_1 = clk_readl(CLK_MISC_CFG_1); /* backup CLK_MISC_CFG_1 value */
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clk_misc_cfg_2 = clk_readl(CLK_MISC_CFG_2); /* backup CLK_MISC_CFG_2 value */
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clk_cfg_val = clk_readl(clk_cfg_reg); /* backup clk_cfg_reg value */
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set_fmeter_divider(k1); /* set divider (0 = /1) */
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set_fmeter_divider_arm(k1);
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clk_writel_mask(clk_cfg_reg, cksw_mask, cksw_val); /* select cksw */
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clk_setl(CLK26CALI_0, tri_bit); /* start fmeter */
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if (wait_fmeter_done(tri_bit)) {
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cnt = clk_readl(cnt_reg) & 0xFFFF;
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freq = (cnt * 25000) * (k1 + 1) / (RG_FRMTR_WINDOW + 1); /* (KHz) ; freq = counter * 26M / 1024 */
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}
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/* restore register settings */
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clk_writel(clk_cfg_reg, clk_cfg_val);
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clk_writel(CLK_MISC_CFG_2, clk_misc_cfg_2);
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clk_writel(CLK_MISC_CFG_1, clk_misc_cfg_1);
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clk_clrl(CLK26CALI_0, BIT(7)); /* disable fmeter_en */
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return freq;
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}
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static u32 measure_stable_fmeter_freq(enum FMETER_TYPE type, int k1, int clk)
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{
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u32 last_freq = 0;
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u32 freq = fmeter_freq(type, k1, clk);
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u32 maxfreq = max(freq, last_freq);
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while (maxfreq > 0 && ABS_DIFF(freq, last_freq) * 100 / maxfreq > 10) {
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last_freq = freq;
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freq = fmeter_freq(type, k1, clk);
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maxfreq = max(freq, last_freq);
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}
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return freq;
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}
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static const struct fmeter_clk *get_all_fmeter_clks(void)
|
|
{
|
|
return fclks;
|
|
}
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|
|
|
struct bak {
|
|
u32 fhctl_hp_en;
|
|
};
|
|
|
|
static void *prepare_fmeter(void)
|
|
{
|
|
static struct bak regs;
|
|
|
|
regs.fhctl_hp_en = clk_readl(FHCTL_HP_EN);
|
|
|
|
clk_writel(FHCTL_HP_EN, 0x0); /* disable PLL hopping */
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|
udelay(10);
|
|
|
|
return ®s;
|
|
}
|
|
|
|
static void unprepare_fmeter(void *data)
|
|
{
|
|
struct bak *regs = data;
|
|
|
|
/* restore old setting */
|
|
clk_writel(FHCTL_HP_EN, regs->fhctl_hp_en);
|
|
}
|
|
|
|
static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
|
|
{
|
|
if (fclk->type)
|
|
return measure_stable_fmeter_freq(fclk->type, 0, fclk->id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* clkdbg dump_state
|
|
*/
|
|
|
|
static const char * const *get_all_clk_names(void)
|
|
{
|
|
static const char * const clks[] = {
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|
/* plls */
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|
"armpll",
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|
"mainpll",
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|
"univ2pll",
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|
"eth1pll",
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|
"eth2pll",
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|
"aud1pll",
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|
"aud2pll",
|
|
"trgpll",
|
|
"sgmipll",
|
|
/* topckgen */
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|
"to_u2_phy",
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|
"to_u2_phy_1p",
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|
"pcie0_pipe_en",
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|
"pcie1_pipe_en",
|
|
"ssusb_tx250m",
|
|
"ssusb_eq_rx250m",
|
|
"ssusb_cdr_ref",
|
|
"ssusb_cdr_fb",
|
|
"sata_asic",
|
|
"sata_rbc",
|
|
"to_usb3_sys",
|
|
"p1_1mhz",
|
|
"free_run_4mhz",
|
|
"p0_1mhz",
|
|
"txclk_src_pre",
|
|
"rtc",
|
|
"mempll",
|
|
"dmpll_ck",
|
|
"syspll_d2",
|
|
"syspll1_d2",
|
|
"syspll1_d4",
|
|
"syspll1_d8",
|
|
"syspll2_d4",
|
|
"syspll2_d8",
|
|
"syspll_d5",
|
|
"syspll3_d2",
|
|
"syspll3_d4",
|
|
"syspll4_d2",
|
|
"syspll4_d4",
|
|
"syspll4_d16",
|
|
"univpll",
|
|
"univpll_d2",
|
|
"univpll1_d2",
|
|
"univpll1_d4",
|
|
"univpll1_d8",
|
|
"univpll1_d16",
|
|
"univpll2_d2",
|
|
"univpll2_d4",
|
|
"univpll2_d8",
|
|
"univpll2_d16",
|
|
"univpll_d5",
|
|
"univpll3_d2",
|
|
"univpll3_d4",
|
|
"univpll3_d16",
|
|
"univpll_d7",
|
|
"univpll_d80_d4",
|
|
"univ48m",
|
|
"sgmiipll_ck",
|
|
"sgmiipll_d2",
|
|
"aud1pll_ck",
|
|
"aud2pll_ck",
|
|
"aud_i2s2_mck",
|
|
"to_usb3_ref",
|
|
"pcie1_mac_en",
|
|
"pcie0_mac_en",
|
|
"eth_500m",
|
|
"axi_sel",
|
|
"mem_sel",
|
|
"ddrphycfg_sel",
|
|
"eth_sel",
|
|
"pwm_sel",
|
|
"f10m_ref_sel",
|
|
"nfi_infra_sel",
|
|
"flash_sel",
|
|
"uart_sel",
|
|
"spi0_sel",
|
|
"spi1_sel",
|
|
"msdc50_0_sel",
|
|
"msdc30_0_sel",
|
|
"msdc30_1_sel",
|
|
"a1sys_hp_sel",
|
|
"a2sys_hp_sel",
|
|
"intdir_sel",
|
|
"aud_intbus_sel",
|
|
"pmicspi_sel",
|
|
"scp_sel",
|
|
"atb_sel",
|
|
"hif_sel",
|
|
"audio_sel",
|
|
"usb20_sel",
|
|
"aud1_sel",
|
|
"aud2_sel",
|
|
"irrx_sel",
|
|
"irtx_sel",
|
|
"asm_l_sel",
|
|
"asm_m_sel",
|
|
"asm_h_sel",
|
|
"apll1_ck_sel",
|
|
"apll2_ck_sel",
|
|
"i2s0_mck_sel",
|
|
"i2s1_mck_sel",
|
|
"i2s2_mck_sel",
|
|
"i2s3_mck_sel",
|
|
"apll1_ck_div",
|
|
"apll2_ck_div",
|
|
"i2s0_mck_div",
|
|
"i2s1_mck_div",
|
|
"i2s2_mck_div",
|
|
"i2s3_mck_div",
|
|
"a1sys_div",
|
|
"a2sys_div",
|
|
"apll1_ck_div_pd",
|
|
"apll2_ck_div_pd",
|
|
"i2s0_mck_div_pd",
|
|
"i2s1_mck_div_pd",
|
|
"i2s2_mck_div_pd",
|
|
"i2s3_mck_div_pd",
|
|
"a1sys_div_pd",
|
|
"a2sys_div_pd",
|
|
/* infracfg */
|
|
"infra_mux1_sel",
|
|
"infra_dbgclk_pd",
|
|
"infra_audio_pd",
|
|
"infra_irrx_pd",
|
|
"infra_apxgpt_pd",
|
|
"infra_pmic_pd",
|
|
/* pericfg */
|
|
"peribus_ck_sel",
|
|
"peri_therm_pd",
|
|
"peri_pwm1_pd",
|
|
"peri_pwm2_pd",
|
|
"peri_pwm3_pd",
|
|
"peri_pwm4_pd",
|
|
"peri_pwm5_pd",
|
|
"peri_pwm6_pd",
|
|
"peri_pwm7_pd",
|
|
"peri_pwm_pd",
|
|
"peri_ap_dma_pd",
|
|
"peri_msdc30_0",
|
|
"peri_msdc30_1",
|
|
"peri_uart0_pd",
|
|
"peri_uart1_pd",
|
|
"peri_uart2_pd",
|
|
"peri_uart3_pd",
|
|
"peri_uart4_pd",
|
|
"peri_btif_pd",
|
|
"peri_i2c0_pd",
|
|
"peri_i2c1_pd",
|
|
"peri_i2c2_pd",
|
|
"peri_spi1_pd",
|
|
"peri_auxadc_pd",
|
|
"peri_spi0_pd",
|
|
"peri_snfi_pd",
|
|
"peri_nfi_pd",
|
|
"peri_nfiecc_pd",
|
|
"peri_flash_pd",
|
|
"peri_irtx_pd",
|
|
/* audiosys */
|
|
"audio_afe",
|
|
"audio_hdmi",
|
|
"audio_spdf",
|
|
"audio_apll",
|
|
"audio_i2sin1",
|
|
"audio_i2sin2",
|
|
"audio_i2sin3",
|
|
"audio_i2sin4",
|
|
"audio_i2so1",
|
|
"audio_i2so2",
|
|
"audio_i2so3",
|
|
"audio_i2so4",
|
|
"audio_asrci1",
|
|
"audio_asrci2",
|
|
"audio_asrco1",
|
|
"audio_asrco2",
|
|
"audio_intdir",
|
|
"audio_a1sys",
|
|
"audio_a2sys",
|
|
"audio_ul1",
|
|
"audio_ul2",
|
|
"audio_ul3",
|
|
"audio_ul4",
|
|
"audio_ul5",
|
|
"audio_ul6",
|
|
"audio_dl1",
|
|
"audio_dl2",
|
|
"audio_dl3",
|
|
"audio_dl4",
|
|
"audio_dl5",
|
|
"audio_dl6",
|
|
"audio_dlmch",
|
|
"audio_arb1",
|
|
"audio_awb",
|
|
"audio_awb2",
|
|
"audio_dai",
|
|
"audio_mod",
|
|
"audio_asrci3",
|
|
"audio_asrci4",
|
|
"audio_asrco3",
|
|
"audio_asrco4",
|
|
"audio_mem_asrc1",
|
|
"audio_mem_asrc2",
|
|
"audio_mem_asrc3",
|
|
"audio_mem_asrc4",
|
|
"audio_mem_asrc5",
|
|
/* ssusbsys */
|
|
"ssusb_u2_phy_1p",
|
|
"ssusb_u2_phy_en",
|
|
"ssusb_ref_en",
|
|
"ssusb_sys_en",
|
|
"ssusb_mcu_en",
|
|
"ssusb_dma_en",
|
|
/* pciesys */
|
|
"pcie_p1_aux_en",
|
|
"pcie_p1_obff_en",
|
|
"pcie_p1_ahb_en",
|
|
"pcie_p1_axi_en",
|
|
"pcie_p1_mac_en",
|
|
"pcie_p1_pipe_en",
|
|
"pcie_p0_aux_en",
|
|
"pcie_p0_obff_en",
|
|
"pcie_p0_ahb_en",
|
|
"pcie_p0_axi_en",
|
|
"pcie_p0_mac_en",
|
|
"pcie_p0_pipe_en",
|
|
"sata_ahb_en",
|
|
"sata_axi_en",
|
|
"sata_asic_en",
|
|
"sata_rbc_en",
|
|
"sata_pm_en",
|
|
/* ethsys */
|
|
"eth_hsdma_en",
|
|
"eth_esw_en",
|
|
"eth_gp2_en",
|
|
"eth_gp1_en",
|
|
"eth_gp0_en",
|
|
/* sgmiisys */
|
|
"sgmii_tx250m_en",
|
|
"sgmii_rx250m_en",
|
|
"sgmii_cdr_ref",
|
|
"sgmii_cdr_fb",
|
|
/* end */
|
|
NULL
|
|
};
|
|
|
|
return clks;
|
|
}
|
|
|
|
/*
|
|
* clkdbg pwr_status
|
|
*/
|
|
|
|
static const char * const *get_pwr_names(void)
|
|
{
|
|
static const char * const pwr_names[] = {
|
|
[24] = "ETHSYS",
|
|
[25] = "HIF0",
|
|
[26] = "HIF1",
|
|
};
|
|
|
|
return pwr_names;
|
|
}
|
|
|
|
/*
|
|
* init functions
|
|
*/
|
|
|
|
static struct clkdbg_ops clkdbg_mt7622_ops = {
|
|
.get_all_fmeter_clks = get_all_fmeter_clks,
|
|
.prepare_fmeter = prepare_fmeter,
|
|
.unprepare_fmeter = unprepare_fmeter,
|
|
.fmeter_freq = fmeter_freq_op,
|
|
.get_all_regnames = get_all_regnames,
|
|
.get_all_clk_names = get_all_clk_names,
|
|
.get_pwr_names = get_pwr_names,
|
|
};
|
|
|
|
static int __init clkdbg_mt7622_init(void)
|
|
{
|
|
if (!of_machine_is_compatible("mediatek,mt7622"))
|
|
return -ENODEV;
|
|
|
|
init_regbase();
|
|
|
|
set_clkdbg_ops(&clkdbg_mt7622_ops);
|
|
|
|
#if DUMP_INIT_STATE
|
|
print_regs();
|
|
print_fmeter_all();
|
|
#endif /* DUMP_INIT_STATE */
|
|
|
|
return 0;
|
|
}
|
|
device_initcall(clkdbg_mt7622_init);
|