f5d825aaa7
Changes in 4.9.220
bus: sunxi-rsb: Return correct data when mixing 16-bit and 8-bit reads
net: vxge: fix wrong __VA_ARGS__ usage
qlcnic: Fix bad kzalloc null test
i2c: st: fix missing struct parameter description
irqchip/versatile-fpga: Handle chained IRQs properly
sched: Avoid scale real weight down to zero
selftests/x86/ptrace_syscall_32: Fix no-vDSO segfault
libata: Remove extra scsi_host_put() in ata_scsi_add_hosts()
gfs2: Don't demote a glock until its revokes are written
x86/boot: Use unsigned comparison for addresses
locking/lockdep: Avoid recursion in lockdep_count_{for,back}ward_deps()
btrfs: remove a BUG_ON() from merge_reloc_roots()
btrfs: track reloc roots based on their commit root bytenr
misc: rtsx: set correct pcr_ops for rts522A
ASoC: fix regwmask
ASoC: dapm: connect virtual mux with default value
ASoC: dpcm: allow start or stop during pause for backend
ASoC: topology: use name_prefix for new kcontrol
usb: gadget: f_fs: Fix use after free issue as part of queue failure
usb: gadget: composite: Inform controller driver of self-powered
ALSA: usb-audio: Add mixer workaround for TRX40 and co
ALSA: hda: Add driver blacklist
ALSA: hda: Fix potential access overflow in beep helper
ALSA: ice1724: Fix invalid access for enumerated ctl items
ALSA: pcm: oss: Fix regression by buffer overflow fix
media: ti-vpe: cal: fix disable_irqs to only the intended target
acpi/x86: ignore unspecified bit positions in the ACPI global lock field
thermal: devfreq_cooling: inline all stubs for CONFIG_DEVFREQ_THERMAL=n
KEYS: reaching the keys quotas correctly
irqchip/versatile-fpga: Apply clear-mask earlier
MIPS: OCTEON: irq: Fix potential NULL pointer dereference
ath9k: Handle txpower changes even when TPC is disabled
signal: Extend exec_id to 64bits
x86/entry/32: Add missing ASM_CLAC to general_protection entry
KVM: s390: vsie: Fix region 1 ASCE sanity shadow address checks
KVM: s390: vsie: Fix delivery of addressing exceptions
KVM: x86: Allocate new rmap and large page tracking when moving memslot
KVM: VMX: Always VMCLEAR in-use VMCSes during crash with kexec support
KVM: VMX: fix crash cleanup when KVM wasn't used
btrfs: drop block from cache on error in relocation
crypto: mxs-dcp - fix scatterlist linearization for hash
ALSA: hda: Initialize power_state field properly
x86/speculation: Remove redundant arch_smt_update() invocation
tools: gpio: Fix out-of-tree build regression
mm: Use fixed constant in page_frag_alloc instead of size + 1
dm verity fec: fix memory leak in verity_fec_dtr
scsi: zfcp: fix missing erp_lock in port recovery trigger for point-to-point
arm64: armv8_deprecated: Fix undef_hook mask for thumb setend
rtc: omap: Use define directive for PIN_CONFIG_ACTIVE_HIGH
ext4: fix a data race at inode->i_blocks
ocfs2: no need try to truncate file beyond i_size
s390/diag: fix display of diagnose call statistics
Input: i8042 - add Acer Aspire 5738z to nomux list
kmod: make request_module() return an error when autoloading is disabled
cpufreq: powernv: Fix use-after-free
hfsplus: fix crash and filesystem corruption when deleting files
libata: Return correct status in sata_pmp_eh_recover_pm() when ATA_DFLAG_DETACH is set
powerpc/64/tm: Don't let userspace set regs->trap via sigreturn
Btrfs: fix crash during unmount due to race with delayed inode workers
drm/dp_mst: Fix clearing payload state on topology disable
drm: Remove PageReserved manipulation from drm_pci_alloc
ipmi: fix hung processes in __get_guid()
powerpc/fsl_booke: Avoid creating duplicate tlb1 entry
misc: echo: Remove unnecessary parentheses and simplify check for zero
mfd: dln2: Fix sanity checking for endpoints
hsr: check protocol version in hsr_newlink()
net: ipv4: devinet: Fix crash when add/del multicast IP with autojoin
net: qrtr: send msgs from local of same id as broadcast
net: ipv6: do not consider routes via gateways for anycast address check
scsi: ufs: Fix ufshcd_hold() caused scheduling while atomic
jbd2: improve comments about freeing data buffers whose page mapping is NULL
ext4: fix incorrect group count in ext4_fill_super error message
ext4: fix incorrect inodes per group in error message
ASoC: Intel: mrfld: fix incorrect check on p->sink
ASoC: Intel: mrfld: return error codes when an error occurs
ALSA: usb-audio: Don't override ignore_ctl_error value from the map
btrfs: check commit root generation in should_ignore_root
mac80211_hwsim: Use kstrndup() in place of kasprintf()
ext4: do not zeroout extents beyond i_disksize
dm flakey: check for null arg_name in parse_features()
kvm: x86: Host feature SSBD doesn't imply guest feature SPEC_CTRL_SSBD
scsi: target: remove boilerplate code
scsi: target: fix hang when multiple threads try to destroy the same iscsi session
tracing: Fix the race between registering 'snapshot' event trigger and triggering 'snapshot' operation
objtool: Fix switch table detection in .text.unlikely
scsi: sg: add sg_remove_request in sg_common_write
ALSA: hda: Don't release card at firmware loading error
video: fbdev: sis: Remove unnecessary parentheses and commented code
drm: NULL pointer dereference [null-pointer-deref] (CWE 476) problem
Revert "gpio: set up initial state from .get_direction()"
wil6210: increase firmware ready timeout
wil6210: fix temperature debugfs
scsi: ufs: make sure all interrupts are processed
scsi: ufs: ufs-qcom: remove broken hci version quirk
wil6210: rate limit wil_rx_refill error
rtc: pm8xxx: Fix issue in RTC write path
wil6210: fix length check in __wmi_send
soc: qcom: smem: Use le32_to_cpu for comparison
of: fix missing kobject init for !SYSFS && OF_DYNAMIC config
arm64: cpu_errata: include required headers
of: unittest: kmemleak in of_unittest_platform_populate()
clk: at91: usb: continue if clk_hw_round_rate() return zero
power: supply: bq27xxx_battery: Silence deferred-probe error
clk: tegra: Fix Tegra PMC clock out parents
NFS: direct.c: Fix memory leak of dreq when nfs_get_lock_context fails
s390/cpuinfo: fix wrong output when CPU0 is offline
powerpc/maple: Fix declaration made after definition
ext4: do not commit super on read-only bdev
percpu_counter: fix a data race at vm_committed_as
compiler.h: fix error in BUILD_BUG_ON() reporting
KVM: s390: vsie: Fix possible race when shadowing region 3 tables
NFS: Fix memory leaks in nfs_pageio_stop_mirroring()
ext2: fix empty body warnings when -Wextra is used
ext2: fix debug reference to ext2_xattr_cache
libnvdimm: Out of bounds read in __nd_ioctl()
iommu/amd: Fix the configuration of GCR3 table root pointer
fbdev: potential information leak in do_fb_ioctl()
tty: evh_bytechan: Fix out of bounds accesses
locktorture: Print ratio of acquisitions, not failures
mtd: lpddr: Fix a double free in probe()
mtd: phram: fix a double free issue in error path
x86/CPU: Add native CPUID variants returning a single datum
x86/microcode/intel: replace sync_core() with native_cpuid_reg(eax)
x86/vdso: Fix lsl operand order
Linux 4.9.220
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I130bead53d151b84c03bac575c0f3760e14538a6
500 lines
10 KiB
ArmAsm
500 lines
10 KiB
ArmAsm
/*
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* This file contains low-level functions for performing various
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* types of TLB invalidations on various processors with no hash
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* table.
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*
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* This file implements the following functions for all no-hash
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* processors. Some aren't implemented for some variants. Some
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* are inline in tlbflush.h
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*
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* - tlbil_va
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* - tlbil_pid
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* - tlbil_all
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* - tlbivax_bcast
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*
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* Code mostly moved over from misc_32.S
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
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* Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor.h>
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#include <asm/bug.h>
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#if defined(CONFIG_40x)
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/*
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* 40x implementation needs only tlbil_va
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*/
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_GLOBAL(__tlbil_va)
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/* We run the search with interrupts disabled because we have to change
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* the PID and I don't want to preempt when that happens.
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*/
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mfmsr r5
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mfspr r6,SPRN_PID
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wrteei 0
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mtspr SPRN_PID,r4
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tlbsx. r3, 0, r3
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mtspr SPRN_PID,r6
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wrtee r5
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bne 1f
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sync
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/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
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* clear. Since 25 is the V bit in the TLB_TAG, loading this value
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* will invalidate the TLB entry. */
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tlbwe r3, r3, TLB_TAG
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isync
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1: blr
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#elif defined(CONFIG_8xx)
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/*
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* Nothing to do for 8xx, everything is inline
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*/
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#elif defined(CONFIG_44x) /* Includes 47x */
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/*
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* 440 implementation uses tlbsx/we for tlbil_va and a full sweep
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* of the TLB for everything else.
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*/
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_GLOBAL(__tlbil_va)
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mfspr r5,SPRN_MMUCR
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mfmsr r10
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/*
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* We write 16 bits of STID since 47x supports that much, we
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* will never be passed out of bounds values on 440 (hopefully)
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*/
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rlwimi r5,r4,0,16,31
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/* We have to run the search with interrupts disabled, otherwise
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* an interrupt which causes a TLB miss can clobber the MMUCR
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* between the mtspr and the tlbsx.
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*
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* Critical and Machine Check interrupts take care of saving
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* and restoring MMUCR, so only normal interrupts have to be
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* taken care of.
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*/
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wrteei 0
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mtspr SPRN_MMUCR,r5
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tlbsx. r6,0,r3
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bne 10f
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sync
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BEGIN_MMU_FTR_SECTION
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b 2f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
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/* On 440 There are only 64 TLB entries, so r3 < 64, which means bit
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* 22, is clear. Since 22 is the V bit in the TLB_PAGEID, loading this
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* value will invalidate the TLB entry.
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*/
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tlbwe r6,r6,PPC44x_TLB_PAGEID
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isync
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10: wrtee r10
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blr
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2:
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#ifdef CONFIG_PPC_47x
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oris r7,r6,0x8000 /* specify way explicitly */
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clrrwi r4,r3,12 /* get an EPN for the hashing with V = 0 */
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ori r4,r4,PPC47x_TLBE_SIZE
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tlbwe r4,r7,0 /* write it */
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isync
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wrtee r10
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blr
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#else /* CONFIG_PPC_47x */
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1: trap
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
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#endif /* !CONFIG_PPC_47x */
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_GLOBAL(_tlbil_all)
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_GLOBAL(_tlbil_pid)
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BEGIN_MMU_FTR_SECTION
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b 2f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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blr
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2:
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#ifdef CONFIG_PPC_47x
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/* 476 variant. There's not simple way to do this, hopefully we'll
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* try to limit the amount of such full invalidates
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*/
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mfmsr r11 /* Interrupts off */
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wrteei 0
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li r3,-1 /* Current set */
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lis r10,tlb_47x_boltmap@h
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ori r10,r10,tlb_47x_boltmap@l
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lis r7,0x8000 /* Specify way explicitly */
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b 9f /* For each set */
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1: li r9,4 /* Number of ways */
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li r4,0 /* Current way */
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li r6,0 /* Default entry value 0 */
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andi. r0,r8,1 /* Check if way 0 is bolted */
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mtctr r9 /* Load way counter */
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bne- 3f /* Bolted, skip loading it */
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2: /* For each way */
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or r5,r3,r4 /* Make way|index for tlbre */
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rlwimi r5,r5,16,8,15 /* Copy index into position */
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tlbre r6,r5,0 /* Read entry */
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3: addis r4,r4,0x2000 /* Next way */
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andi. r0,r6,PPC47x_TLB0_VALID /* Valid entry ? */
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beq 4f /* Nope, skip it */
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rlwimi r7,r5,0,1,2 /* Insert way number */
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rlwinm r6,r6,0,21,19 /* Clear V */
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tlbwe r6,r7,0 /* Write it */
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4: bdnz 2b /* Loop for each way */
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srwi r8,r8,1 /* Next boltmap bit */
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9: cmpwi cr1,r3,255 /* Last set done ? */
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addi r3,r3,1 /* Next set */
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beq cr1,1f /* End of loop */
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andi. r0,r3,0x1f /* Need to load a new boltmap word ? */
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bne 1b /* No, loop */
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lwz r8,0(r10) /* Load boltmap entry */
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addi r10,r10,4 /* Next word */
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b 1b /* Then loop */
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1: isync /* Sync shadows */
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wrtee r11
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#else /* CONFIG_PPC_47x */
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1: trap
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
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#endif /* !CONFIG_PPC_47x */
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blr
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#ifdef CONFIG_PPC_47x
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/*
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* _tlbivax_bcast is only on 47x. We don't bother doing a runtime
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* check though, it will blow up soon enough if we mistakenly try
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* to use it on a 440.
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*/
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_GLOBAL(_tlbivax_bcast)
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mfspr r5,SPRN_MMUCR
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mfmsr r10
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rlwimi r5,r4,0,16,31
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wrteei 0
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mtspr SPRN_MMUCR,r5
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isync
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PPC_TLBIVAX(0, R3)
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isync
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eieio
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tlbsync
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BEGIN_FTR_SECTION
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b 1f
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END_FTR_SECTION_IFSET(CPU_FTR_476_DD2)
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sync
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wrtee r10
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blr
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/*
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* DD2 HW could hang if in instruction fetch happens before msync completes.
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* Touch enough instruction cache lines to ensure cache hits
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*/
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1: mflr r9
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bl 2f
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2: mflr r6
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li r7,32
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PPC_ICBT(0,R6,R7) /* touch next cache line */
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add r6,r6,r7
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PPC_ICBT(0,R6,R7) /* touch next cache line */
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add r6,r6,r7
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PPC_ICBT(0,R6,R7) /* touch next cache line */
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sync
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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mtlr r9
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wrtee r10
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blr
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#endif /* CONFIG_PPC_47x */
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#elif defined(CONFIG_FSL_BOOKE)
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/*
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* FSL BookE implementations.
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*
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* Since feature sections are using _SECTION_ELSE we need
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* to have the larger code path before the _SECTION_ELSE
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*/
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/*
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* Flush MMU TLB on the local processor
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*/
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_GLOBAL(_tlbil_all)
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BEGIN_MMU_FTR_SECTION
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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MMU_FTR_SECTION_ELSE
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PPC_TLBILX_ALL(0,R0)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
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msync
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isync
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blr
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_GLOBAL(_tlbil_pid)
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BEGIN_MMU_FTR_SECTION
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slwi r3,r3,16
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mfmsr r10
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wrteei 0
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mfspr r4,SPRN_MAS6 /* save MAS6 */
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mtspr SPRN_MAS6,r3
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PPC_TLBILX_PID(0,R0)
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mtspr SPRN_MAS6,r4 /* restore MAS6 */
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wrtee r10
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MMU_FTR_SECTION_ELSE
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
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msync
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isync
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blr
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/*
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* Flush MMU TLB for a particular address, but only on the local processor
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* (no broadcast)
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*/
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_GLOBAL(__tlbil_va)
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mfmsr r10
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wrteei 0
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slwi r4,r4,16
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ori r4,r4,(MAS6_ISIZE(BOOK3E_PAGESZ_4K))@l
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mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
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BEGIN_MMU_FTR_SECTION
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tlbsx 0,r3
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mfspr r4,SPRN_MAS1 /* check valid */
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andis. r3,r4,MAS1_VALID@h
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beq 1f
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rlwinm r4,r4,0,1,31
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mtspr SPRN_MAS1,r4
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tlbwe
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MMU_FTR_SECTION_ELSE
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PPC_TLBILX_VA(0,R3)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
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msync
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isync
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1: wrtee r10
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blr
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#elif defined(CONFIG_PPC_BOOK3E)
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/*
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* New Book3E (>= 2.06) implementation
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*
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* Note: We may be able to get away without the interrupt masking stuff
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* if we save/restore MAS6 on exceptions that might modify it
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*/
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_GLOBAL(_tlbil_pid)
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slwi r4,r3,MAS6_SPID_SHIFT
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mfmsr r10
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wrteei 0
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mtspr SPRN_MAS6,r4
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PPC_TLBILX_PID(0,R0)
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wrtee r10
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msync
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isync
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blr
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_GLOBAL(_tlbil_pid_noind)
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slwi r4,r3,MAS6_SPID_SHIFT
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mfmsr r10
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ori r4,r4,MAS6_SIND
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wrteei 0
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mtspr SPRN_MAS6,r4
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PPC_TLBILX_PID(0,R0)
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wrtee r10
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msync
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isync
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blr
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_GLOBAL(_tlbil_all)
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PPC_TLBILX_ALL(0,R0)
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msync
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isync
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blr
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_GLOBAL(_tlbil_va)
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mfmsr r10
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wrteei 0
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cmpwi cr0,r6,0
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slwi r4,r4,MAS6_SPID_SHIFT
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rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
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beq 1f
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rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
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1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
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PPC_TLBILX_VA(0,R3)
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msync
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isync
|
|
wrtee r10
|
|
blr
|
|
|
|
_GLOBAL(_tlbivax_bcast)
|
|
mfmsr r10
|
|
wrteei 0
|
|
cmpwi cr0,r6,0
|
|
slwi r4,r4,MAS6_SPID_SHIFT
|
|
rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
|
|
beq 1f
|
|
rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
|
|
1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
|
|
PPC_TLBIVAX(0,R3)
|
|
eieio
|
|
tlbsync
|
|
sync
|
|
wrtee r10
|
|
blr
|
|
|
|
_GLOBAL(set_context)
|
|
#ifdef CONFIG_BDI_SWITCH
|
|
/* Context switch the PTE pointer for the Abatron BDI2000.
|
|
* The PGDIR is the second parameter.
|
|
*/
|
|
lis r5, abatron_pteptrs@h
|
|
ori r5, r5, abatron_pteptrs@l
|
|
stw r4, 0x4(r5)
|
|
#endif
|
|
mtspr SPRN_PID,r3
|
|
isync /* Force context change */
|
|
blr
|
|
#else
|
|
#error Unsupported processor type !
|
|
#endif
|
|
|
|
#if defined(CONFIG_PPC_FSL_BOOK3E)
|
|
/*
|
|
* extern void loadcam_entry(unsigned int index)
|
|
*
|
|
* Load TLBCAM[index] entry in to the L2 CAM MMU
|
|
* Must preserve r7, r8, r9, r10 and r11
|
|
*/
|
|
_GLOBAL(loadcam_entry)
|
|
mflr r5
|
|
LOAD_REG_ADDR_PIC(r4, TLBCAM)
|
|
mtlr r5
|
|
mulli r5,r3,TLBCAM_SIZE
|
|
add r3,r5,r4
|
|
lwz r4,TLBCAM_MAS0(r3)
|
|
mtspr SPRN_MAS0,r4
|
|
lwz r4,TLBCAM_MAS1(r3)
|
|
mtspr SPRN_MAS1,r4
|
|
PPC_LL r4,TLBCAM_MAS2(r3)
|
|
mtspr SPRN_MAS2,r4
|
|
lwz r4,TLBCAM_MAS3(r3)
|
|
mtspr SPRN_MAS3,r4
|
|
BEGIN_MMU_FTR_SECTION
|
|
lwz r4,TLBCAM_MAS7(r3)
|
|
mtspr SPRN_MAS7,r4
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
|
|
isync
|
|
tlbwe
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Load multiple TLB entries at once, using an alternate-space
|
|
* trampoline so that we don't have to care about whether the same
|
|
* TLB entry maps us before and after.
|
|
*
|
|
* r3 = first entry to write
|
|
* r4 = number of entries to write
|
|
* r5 = temporary tlb entry
|
|
*/
|
|
_GLOBAL(loadcam_multi)
|
|
mflr r8
|
|
/* Don't switch to AS=1 if already there */
|
|
mfmsr r11
|
|
andi. r11,r11,MSR_IS
|
|
bne 10f
|
|
|
|
/*
|
|
* Set up temporary TLB entry that is the same as what we're
|
|
* running from, but in AS=1.
|
|
*/
|
|
bl 1f
|
|
1: mflr r6
|
|
tlbsx 0,r8
|
|
mfspr r6,SPRN_MAS1
|
|
ori r6,r6,MAS1_TS
|
|
mtspr SPRN_MAS1,r6
|
|
mfspr r6,SPRN_MAS0
|
|
rlwimi r6,r5,MAS0_ESEL_SHIFT,MAS0_ESEL_MASK
|
|
mr r7,r5
|
|
mtspr SPRN_MAS0,r6
|
|
isync
|
|
tlbwe
|
|
isync
|
|
|
|
/* Switch to AS=1 */
|
|
mfmsr r6
|
|
ori r6,r6,MSR_IS|MSR_DS
|
|
mtmsr r6
|
|
isync
|
|
|
|
10:
|
|
mr r9,r3
|
|
add r10,r3,r4
|
|
2: bl loadcam_entry
|
|
addi r9,r9,1
|
|
cmpw r9,r10
|
|
mr r3,r9
|
|
blt 2b
|
|
|
|
/* Don't return to AS=0 if we were in AS=1 at function start */
|
|
andi. r11,r11,MSR_IS
|
|
bne 3f
|
|
|
|
/* Return to AS=0 and clear the temporary entry */
|
|
mfmsr r6
|
|
rlwinm. r6,r6,0,~(MSR_IS|MSR_DS)
|
|
mtmsr r6
|
|
isync
|
|
|
|
li r6,0
|
|
mtspr SPRN_MAS1,r6
|
|
rlwinm r6,r7,MAS0_ESEL_SHIFT,MAS0_ESEL_MASK
|
|
oris r6,r6,MAS0_TLBSEL(1)@h
|
|
mtspr SPRN_MAS0,r6
|
|
isync
|
|
tlbwe
|
|
isync
|
|
|
|
3:
|
|
mtlr r8
|
|
blr
|
|
#endif
|