Changes in 4.9.232 pinctrl: amd: fix npins for uart0 in kerncz_groups mac80211: allow rx of mesh eapol frames with default rx key scsi: scsi_transport_spi: Fix function pointer check xtensa: fix __sync_fetch_and_{and,or}_4 declarations xtensa: update *pos in cpuinfo_op.next drivers/net/wan/lapbether: Fixed the value of hard_header_len net: sky2: initialize return of gm_phy_read drm/nouveau/i2c/g94-: increase NV_PMGR_DP_AUXCTL_TRANSACTREQ timeout SUNRPC reverting d03727b248d0 ("NFSv4 fix CLOSE not waiting for direct IO compeletion") uprobes: Change handle_swbp() to send SIGTRAP with si_code=SI_KERNEL, to fix GDB regression ALSA: info: Drop WARN_ON() from buffer NULL sanity check ASoC: rt5670: Correct RT5670_LDO_SEL_MASK btrfs: fix double free on ulist after backref resolution failure btrfs: fix mount failure caused by race with umount bnxt_en: Fix race when modifying pause settings. hippi: Fix a size used in a 'pci_free_consistent()' in an error handling path ax88172a: fix ax88172a_unbind() failures net: dp83640: fix SIOCSHWTSTAMP to update the struct with actual configuration net: smc91x: Fix possible memory leak in smc_drv_probe() scripts/decode_stacktrace: strip basepath from all paths HID: i2c-hid: add Mediacom FlexBook edge13 to descriptor override HID: apple: Disable Fn-key key-re-mapping on clone keyboards dmaengine: tegra210-adma: Fix runtime PM imbalance on error regmap: dev_get_regmap_match(): fix string comparison dmaengine: ioat setting ioat timeout as module parameter usb: gadget: udc: gr_udc: fix memleak on error handling path in gr_ep_init() arm64: Use test_tsk_thread_flag() for checking TIF_SINGLESTEP x86: math-emu: Fix up 'cmp' insn for clang ias usb: xhci-mtk: fix the failure of bandwidth allocation usb: xhci: Fix ASM2142/ASM3142 DMA addressing Revert "cifs: Fix the target file was deleted when rename failed." staging: wlan-ng: properly check endpoint types staging: comedi: addi_apci_1032: check INSN_CONFIG_DIGITAL_TRIG shift staging: comedi: ni_6527: fix INSN_CONFIG_DIGITAL_TRIG support staging: comedi: addi_apci_1500: check INSN_CONFIG_DIGITAL_TRIG shift staging: comedi: addi_apci_1564: check INSN_CONFIG_DIGITAL_TRIG shift serial: 8250: fix null-ptr-deref in serial8250_start_tx() serial: 8250_mtk: Fix high-speed baud rates clamping vt: Reject zero-sized screen buffer size. Makefile: Fix GCC_TOOLCHAIN_DIR prefix for Clang cross compilation mm/memcg: fix refcount error while moving and swapping io-mapping: indicate mapping failure parisc: Add atomic64_set_release() define to avoid CPU soft lockups ath9k: Fix general protection fault in ath9k_hif_usb_rx_cb ath9k: Fix regression with Atheros 9271 AX.25: Fix out-of-bounds read in ax25_connect() AX.25: Prevent out-of-bounds read in ax25_sendmsg() dev: Defer free of skbs in flush_backlog net-sysfs: add a newline when printing 'tx_timeout' by sysfs net: udp: Fix wrong clean up for IS_UDPLITE macro rxrpc: Fix sendmsg() returning EPIPE due to recvmsg() returning ENODATA AX.25: Prevent integer overflows in connect and sendmsg tcp: allow at most one TLP probe per flight ip6_gre: fix null-ptr-deref in ip6gre_init_net() drivers/net/wan/x25_asy: Fix to make it work regmap: debugfs: check count when read regmap file xfs: set format back to extents if xfs_bmap_extents_to_btree perf probe: Fix to check blacklist address correctly perf annotate: Use asprintf when formatting objdump command line perf tools: Fix snprint warnings for gcc 8 perf: Make perf able to build with latest libbfd Linux 4.9.232 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: Iae57e72dbaebe67399c6756146f30762e5f25b2e
336 lines
8.1 KiB
C
336 lines
8.1 KiB
C
/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
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* Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
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*/
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#ifndef _ASM_PARISC_ATOMIC_H_
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#define _ASM_PARISC_ATOMIC_H_
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#include <linux/types.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* And probably incredibly slow on parisc. OTOH, we don't
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* have to write any serious assembly. prumpf
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*/
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#ifdef CONFIG_SMP
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#include <asm/spinlock.h>
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#include <asm/cache.h> /* we use L1_CACHE_BYTES */
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/* Use an array of spinlocks for our atomic_ts.
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* Hash function to index into a different SPINLOCK.
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* Since "a" is usually an address, use one spinlock per cacheline.
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*/
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# define ATOMIC_HASH_SIZE 4
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# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a))/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
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extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
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/* Can't use raw_spin_lock_irq because of #include problems, so
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* this is the substitute */
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#define _atomic_spin_lock_irqsave(l,f) do { \
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arch_spinlock_t *s = ATOMIC_HASH(l); \
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local_irq_save(f); \
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arch_spin_lock(s); \
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} while(0)
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#define _atomic_spin_unlock_irqrestore(l,f) do { \
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arch_spinlock_t *s = ATOMIC_HASH(l); \
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arch_spin_unlock(s); \
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local_irq_restore(f); \
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} while(0)
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#else
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# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
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# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
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#endif
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/*
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* Note that we need not lock read accesses - aligned word writes/reads
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* are atomic, so a reader never sees inconsistent values.
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*/
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static __inline__ void atomic_set(atomic_t *v, int i)
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{
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unsigned long flags;
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_atomic_spin_lock_irqsave(v, flags);
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v->counter = i;
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_atomic_spin_unlock_irqrestore(v, flags);
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}
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static __inline__ int atomic_read(const atomic_t *v)
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{
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return READ_ONCE((v)->counter);
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}
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/* exported interface */
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#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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/**
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* __atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int c, old;
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c = atomic_read(v);
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for (;;) {
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if (unlikely(c == (u)))
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break;
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old = atomic_cmpxchg((v), c, c + (a));
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if (likely(old == c))
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break;
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c = old;
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}
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return c;
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}
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#define ATOMIC_OP(op, c_op) \
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static __inline__ void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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\
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_atomic_spin_lock_irqsave(v, flags); \
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v->counter c_op i; \
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_atomic_spin_unlock_irqrestore(v, flags); \
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} \
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#define ATOMIC_OP_RETURN(op, c_op) \
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static __inline__ int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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int ret; \
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\
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_atomic_spin_lock_irqsave(v, flags); \
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ret = (v->counter c_op i); \
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_atomic_spin_unlock_irqrestore(v, flags); \
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\
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return ret; \
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}
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#define ATOMIC_FETCH_OP(op, c_op) \
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static __inline__ int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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int ret; \
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\
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_atomic_spin_lock_irqsave(v, flags); \
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ret = v->counter; \
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v->counter c_op i; \
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_atomic_spin_unlock_irqrestore(v, flags); \
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\
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return ret; \
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}
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#define ATOMIC_OPS(op, c_op) \
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ATOMIC_OP(op, c_op) \
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ATOMIC_OP_RETURN(op, c_op) \
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ATOMIC_FETCH_OP(op, c_op)
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ATOMIC_OPS(add, +=)
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ATOMIC_OPS(sub, -=)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op) \
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ATOMIC_OP(op, c_op) \
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ATOMIC_FETCH_OP(op, c_op)
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ATOMIC_OPS(and, &=)
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ATOMIC_OPS(or, |=)
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ATOMIC_OPS(xor, ^=)
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#define atomic_inc(v) (atomic_add( 1,(v)))
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#define atomic_dec(v) (atomic_add( -1,(v)))
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#define atomic_inc_return(v) (atomic_add_return( 1,(v)))
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#define atomic_dec_return(v) (atomic_add_return( -1,(v)))
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
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#define ATOMIC_INIT(i) { (i) }
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#ifdef CONFIG_64BIT
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#define ATOMIC64_INIT(i) { (i) }
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#define ATOMIC64_OP(op, c_op) \
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static __inline__ void atomic64_##op(s64 i, atomic64_t *v) \
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{ \
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unsigned long flags; \
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\
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_atomic_spin_lock_irqsave(v, flags); \
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v->counter c_op i; \
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_atomic_spin_unlock_irqrestore(v, flags); \
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} \
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#define ATOMIC64_OP_RETURN(op, c_op) \
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static __inline__ s64 atomic64_##op##_return(s64 i, atomic64_t *v) \
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{ \
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unsigned long flags; \
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s64 ret; \
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\
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_atomic_spin_lock_irqsave(v, flags); \
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ret = (v->counter c_op i); \
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_atomic_spin_unlock_irqrestore(v, flags); \
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\
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return ret; \
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}
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#define ATOMIC64_FETCH_OP(op, c_op) \
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static __inline__ s64 atomic64_fetch_##op(s64 i, atomic64_t *v) \
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{ \
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unsigned long flags; \
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s64 ret; \
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\
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_atomic_spin_lock_irqsave(v, flags); \
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ret = v->counter; \
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v->counter c_op i; \
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_atomic_spin_unlock_irqrestore(v, flags); \
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\
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return ret; \
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}
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#define ATOMIC64_OPS(op, c_op) \
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ATOMIC64_OP(op, c_op) \
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ATOMIC64_OP_RETURN(op, c_op) \
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ATOMIC64_FETCH_OP(op, c_op)
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ATOMIC64_OPS(add, +=)
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ATOMIC64_OPS(sub, -=)
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, c_op) \
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ATOMIC64_OP(op, c_op) \
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ATOMIC64_FETCH_OP(op, c_op)
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ATOMIC64_OPS(and, &=)
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ATOMIC64_OPS(or, |=)
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ATOMIC64_OPS(xor, ^=)
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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static __inline__ void
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atomic64_set(atomic64_t *v, s64 i)
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{
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unsigned long flags;
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_atomic_spin_lock_irqsave(v, flags);
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v->counter = i;
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_atomic_spin_unlock_irqrestore(v, flags);
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}
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#define atomic64_set_release(v, i) atomic64_set((v), (i))
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static __inline__ s64
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atomic64_read(const atomic64_t *v)
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{
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return ACCESS_ONCE((v)->counter);
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}
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#define atomic64_inc(v) (atomic64_add( 1,(v)))
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#define atomic64_dec(v) (atomic64_add( -1,(v)))
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#define atomic64_inc_return(v) (atomic64_add_return( 1,(v)))
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#define atomic64_dec_return(v) (atomic64_add_return( -1,(v)))
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
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#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i),(v)) == 0)
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/* exported interface */
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#define atomic64_cmpxchg(v, o, n) \
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((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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/**
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* atomic64_add_unless - add unless the number is a given value
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* @v: pointer of type atomic64_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long c, old;
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c = atomic64_read(v);
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for (;;) {
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if (unlikely(c == (u)))
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break;
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old = atomic64_cmpxchg((v), c, c + (a));
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if (likely(old == c))
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break;
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c = old;
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}
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return c != (u);
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}
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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/*
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* atomic64_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic_t
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*
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* The function returns the old value of *v minus 1, even if
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* the atomic variable, v, was not decremented.
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*/
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static inline long atomic64_dec_if_positive(atomic64_t *v)
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{
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long c, old, dec;
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c = atomic64_read(v);
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for (;;) {
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dec = c - 1;
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if (unlikely(dec < 0))
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break;
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old = atomic64_cmpxchg((v), c, dec);
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if (likely(old == c))
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break;
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c = old;
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}
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return dec;
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}
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#endif /* !CONFIG_64BIT */
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#endif /* _ASM_PARISC_ATOMIC_H_ */
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