0835e6ca5d
Also: - move IPPC doorbell fixup to xhci-mtk - wait for U3 MAC clock ready after xhci_reset (en75xx issue)
215 lines
6.0 KiB
C
215 lines
6.0 KiB
C
#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/rt2880/rt_mmap.h>
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#if defined(CONFIG_RALINK_MT7621)
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#define ADDR_SIFSLV_BASE RALINK_XHCI_UPHY_BASE
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#define ADDR_SIFSLV_FMREG_BASE (ADDR_SIFSLV_BASE+0x0100)
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#define ADDR_U2_PHY_P0_BASE (ADDR_SIFSLV_BASE+0x0800)
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#define ADDR_U2_PHY_P1_BASE (ADDR_SIFSLV_BASE+0x1000)
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#define U2_SR_COEFF 28
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#elif defined(CONFIG_RALINK_MT7628)
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#define ADDR_SIFSLV_FMREG_BASE (RALINK_USB_DEV_BASE+0xf00)
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#define ADDR_U2_PHY_P0_BASE (RALINK_USB_DEV_BASE+0x800)
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#define U2_SR_COEFF 32
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#endif
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#define REG_SIFSLV_FMREG_FMCR0 (ADDR_SIFSLV_FMREG_BASE+0x00)
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#define REG_SIFSLV_FMREG_FMCR1 (ADDR_SIFSLV_FMREG_BASE+0x04)
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#define REG_SIFSLV_FMREG_FMCR2 (ADDR_SIFSLV_FMREG_BASE+0x08)
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#define REG_SIFSLV_FMREG_FMMONR0 (ADDR_SIFSLV_FMREG_BASE+0x0C)
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#define REG_SIFSLV_FMREG_FMMONR1 (ADDR_SIFSLV_FMREG_BASE+0x10)
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/* SIFSLV_FMREG_FMCR0 */
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#define RG_LOCKTH (0xf<<28)
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#define RG_MONCLK_SEL (0x3<<26)
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#define RG_FM_MODE (0x1<<25)
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#define RG_FREQDET_EN (0x1<<24)
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#define RG_CYCLECNT (0x00ffffff)
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/* SIFSLV_FMREG_FMMONR1 */
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#define RG_MONCLK_SEL_3 (0x1<<9)
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#define RG_FRCK_EN (0x1<<8)
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#define USBPLL_LOCK (0x1<<1)
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#define USB_FM_VLD (0x1<<0)
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#define OFS_U2_PHY_AC0 0x00
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#define OFS_U2_PHY_AC1 0x04
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#define OFS_U2_PHY_AC2 0x08
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#define OFS_U2_PHY_ACR0 0x10
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#define OFS_U2_PHY_ACR1 0x14
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#define OFS_U2_PHY_ACR2 0x18
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#define OFS_U2_PHY_ACR3 0x1C
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#define OFS_U2_PHY_ACR4 0x20
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#define OFS_U2_PHY_AMON0 0x24
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#define OFS_U2_PHY_DCR0 0x60
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#define OFS_U2_PHY_DCR1 0x64
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#define OFS_U2_PHY_DTM0 0x68
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#define OFS_U2_PHY_DTM1 0x6C
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/* U2_PHY_ACR0 */
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#define RG_USB20_ICUSB_EN (0x1<<24)
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#define RG_USB20_HSTX_SRCAL_EN (0x1<<23)
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#define RG_USB20_HSTX_SRCTRL (0x7<<16)
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#define RG_USB20_LS_CR (0x7<<12)
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#define RG_USB20_FS_CR (0x7<<8)
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#define RG_USB20_LS_SR (0x7<<4)
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#define RG_USB20_FS_SR (0x7<<0)
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static atomic_t uphy_init_instance = ATOMIC_INIT(0);
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static void
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u2_slew_rate_calibration(int port_id, u32 u2_phy_reg_base)
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{
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int i;
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u32 reg_val;
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u32 u4FmOut = 0;
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// => RG_USB20_HSTX_SRCAL_EN = 1
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// enable HS TX SR calibration
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reg_val = sysRegRead(u2_phy_reg_base + OFS_U2_PHY_ACR0);
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reg_val |= RG_USB20_HSTX_SRCAL_EN;
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sysRegWrite(u2_phy_reg_base + OFS_U2_PHY_ACR0, reg_val);
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msleep(1);
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// => RG_FRCK_EN = 1
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// Enable free run clock
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reg_val = sysRegRead(REG_SIFSLV_FMREG_FMMONR1);
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reg_val |= RG_FRCK_EN;
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sysRegWrite(REG_SIFSLV_FMREG_FMMONR1, reg_val);
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// MT6290 HS signal quality patch
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// => RG_CYCLECNT = 400
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// Setting cyclecnt = 400
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reg_val = sysRegRead(REG_SIFSLV_FMREG_FMCR0);
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reg_val &= ~RG_CYCLECNT;
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reg_val |= 0x400;
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sysRegWrite(REG_SIFSLV_FMREG_FMCR0, reg_val);
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// => RG_FREQDET_EN = 1
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// Enable frequency meter
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reg_val = sysRegRead(REG_SIFSLV_FMREG_FMCR0);
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reg_val |= RG_FREQDET_EN;
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sysRegWrite(REG_SIFSLV_FMREG_FMCR0, reg_val);
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// wait for FM detection done, set 10ms timeout
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for (i = 0; i < 10; i++) {
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// => u4FmOut = USB_FM_OUT
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// read FM_OUT
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u4FmOut = sysRegRead(REG_SIFSLV_FMREG_FMMONR0);
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// check if FM detection done
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if (u4FmOut != 0)
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break;
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msleep(1);
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}
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// => RG_FREQDET_EN = 0
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// disable frequency meter
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reg_val = sysRegRead(REG_SIFSLV_FMREG_FMCR0);
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reg_val &= ~RG_FREQDET_EN;
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sysRegWrite(REG_SIFSLV_FMREG_FMCR0, reg_val);
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// => RG_FRCK_EN = 0
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// disable free run clock
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reg_val = sysRegRead(REG_SIFSLV_FMREG_FMMONR1);
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reg_val &= ~RG_FRCK_EN;
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sysRegWrite(REG_SIFSLV_FMREG_FMMONR1, reg_val);
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// => RG_USB20_HSTX_SRCAL_EN = 0
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// disable HS TX SR calibration
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reg_val = sysRegRead(u2_phy_reg_base + OFS_U2_PHY_ACR0);
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reg_val &= ~RG_USB20_HSTX_SRCAL_EN;
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sysRegWrite(u2_phy_reg_base + OFS_U2_PHY_ACR0, reg_val);
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msleep(1);
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// => RG_USB20_HSTX_SRCTRL
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reg_val = sysRegRead(u2_phy_reg_base + OFS_U2_PHY_ACR0);
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reg_val &= ~RG_USB20_HSTX_SRCTRL;
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if (u4FmOut != 0) {
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// set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
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u32 u4Tmp = (((1024 * 25 * U2_SR_COEFF) / u4FmOut) + 500) / 1000;
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reg_val |= ((u4Tmp & 0x07)<<16);
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printk(KERN_INFO "U2PHY P%d set SRCTRL %s value: %d\n", port_id, "calibration", u4Tmp);
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} else {
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reg_val |= (0x4<<16);
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printk(KERN_INFO "U2PHY P%d set SRCTRL %s value: %d\n", port_id, "default", 4);
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}
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sysRegWrite(u2_phy_reg_base + OFS_U2_PHY_ACR0, reg_val);
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}
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#if defined(CONFIG_RALINK_MT7621)
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static void
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u2_phy_init(u32 u2_phy_reg_base)
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{
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u32 reg_val;
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/* set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
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reg_val = sysRegRead(u2_phy_reg_base + OFS_U2_PHY_DCR1);
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reg_val &= ~(0x3 << 18);
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reg_val |= (0x1 << 18);
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sysRegWrite(u2_phy_reg_base + OFS_U2_PHY_DCR1, reg_val);
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}
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void
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uphy_init(void)
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{
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if (atomic_inc_return(&uphy_init_instance) != 1)
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return;
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u2_phy_init(ADDR_U2_PHY_P0_BASE);
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u2_phy_init(ADDR_U2_PHY_P1_BASE);
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u2_slew_rate_calibration(0, ADDR_U2_PHY_P0_BASE);
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u2_slew_rate_calibration(1, ADDR_U2_PHY_P1_BASE);
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}
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#elif defined(CONFIG_RALINK_MT7628)
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static inline void
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u2_phy_init(void)
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{
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u32 reg_val;
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reg_val = sysRegRead(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_AC2);
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reg_val = sysRegRead(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_ACR0);
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reg_val = sysRegRead(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0);
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sysRegWrite(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0, 0x00ffff02);
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reg_val = sysRegRead(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0);
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sysRegWrite(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0, 0x00555502);
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reg_val = sysRegRead(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0);
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sysRegWrite(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0, 0x00aaaa02);
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reg_val = sysRegRead(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0);
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sysRegWrite(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0, 0x00000402);
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reg_val = sysRegRead(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DCR0);
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sysRegWrite(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_AC0, 0x0048086a);
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sysRegWrite(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_AC1, 0x4400001c);
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sysRegWrite(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_ACR3, 0xc0200000);
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sysRegWrite(ADDR_U2_PHY_P0_BASE + OFS_U2_PHY_DTM0, 0x02000000);
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}
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void
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uphy_init(void)
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{
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if (atomic_inc_return(&uphy_init_instance) != 1)
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return;
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u2_phy_init();
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u2_slew_rate_calibration(0, ADDR_U2_PHY_P0_BASE);
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}
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#endif
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