64 lines
1.2 KiB
C
64 lines
1.2 KiB
C
#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <asm/setup.h>
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#include <asm/irq_cpu.h>
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#include <asm/rt2880/rt_mmap.h>
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#ifndef CONFIG_CLKSRC_MIPS_GIC
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unsigned int get_c0_compare_int(void)
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{
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return gic_get_c0_compare_int();
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}
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#endif
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#if IS_ENABLED(CONFIG_HW_PERF_EVENTS) || IS_ENABLED(CONFIG_OPROFILE)
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int get_c0_perfcount_int(void)
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{
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/*
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* Performance counter events are routed through GIC.
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* Prevent them from firing on CPU IRQ7 as well
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*/
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clear_c0_status(IE_SW0 << 7);
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return gic_get_c0_perfcount_int();
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}
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EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
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#endif
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#ifdef CONFIG_MIPS_EJTAG_FDC_TTY
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int get_c0_fdc_int(void)
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{
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return gic_get_c0_fdc_int();
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}
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#endif
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void mtk_disable_irq_all(void)
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{
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}
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void __init arch_init_irq(void)
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{
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phys_addr_t gic_base = RALINK_GIC_BASE;
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size_t gic_len = RALINK_GIC_ADDRSPACE_SZ;
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mips_cpu_irq_init();
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if (mips_cm_present()) {
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gic_base = read_gcr_gic_base() & ~CM_GCR_GIC_BASE_GICEN_MSK;
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write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
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__sync();
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}
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gic_present = true;
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gic_init(gic_base, gic_len, GIC_CPU_PIN_OFFSET, 0);
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/* set EDGE type int for MT7530 MCM (prevent race) */
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irq_set_irq_type(SURFBOARDINT_ESW, IRQ_TYPE_EDGE_RISING);
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}
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