80 lines
3.2 KiB
C
80 lines
3.2 KiB
C
/*
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* Copyright (C) 2001 Palmchip Corporation. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Defines for the Surfboard interrupt controller.
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*
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*/
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#ifndef __ASM_MACH_MIPS_TC3262_SURFBOARDINT_H
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#define __ASM_MACH_MIPS_TC3262_SURFBOARDINT_H
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#include "tc3262_int_source.h"
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#if defined(CONFIG_MIPS_TC3262_1004K)
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/* MIPS GIC controller (via EIC) */
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#define GIC_NUM_INTRS 64
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0)
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#define SURFBOARDINT_UART_LITE1 UART_INT /* UART Lite1 */
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#define SURFBOARDINT_TIMER0 TIMER0_INT, /* Timer0 */
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#define SURFBOARDINT_TIMER1 TIMER1_INT /* Timer1 */
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#define SURFBOARDINT_TIMER2 TIMER2_INT /* Timer2 */
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#define SURFBOARDINT_WDG TIMER5_INT /* WDG timer */
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#define SURFBOARDINT_GPIO GPIO_INT /* GPIO */
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#define SURFBOARDINT_PCM PCM1_INT /* PCM */
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#define SURFBOARDINT_ESW MAC1_INT /* ESW */
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#define SURFBOARDINT_UART_LITE2 UART2_INT /* UART Lite2 */
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#define SURFBOARDINT_USB IRQ_RT3XXX_USB /* USB */
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#define SURFBOARDINT_DMT DMT_INT /* xDSL DMT */
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#define SURFBOARDINT_QDMA1 QDMA_LAN0_INTR /* QDMA1, INT0 */
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#define SURFBOARDINT_QDMA2 QDMA_WAN0_INTR /* QDMA2, INT0 */
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#define SURFBOARDINT_PCIE0 PCIE_0_INT /* PCIE0 */
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#define SURFBOARDINT_PCIE1 PCIE_A_INT /* PCIE1 */
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#define SURFBOARDINT_CRYPTO CRYPTO_INT /* CryptoEngine */
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#define SURFBOARDINT_QDMA1_INT1 QDMA_LAN1_INTR /* QDMA1, INT1 */
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#define SURFBOARDINT_QDMA1_INT2 QDMA_LAN2_INTR /* QDMA1, INT2 */
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#define SURFBOARDINT_QDMA1_INT3 QDMA_LAN3_INTR /* QDMA1, INT3 */
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#define SURFBOARDINT_QDMA2_INT1 QDMA_WAN1_INTR /* QDMA2, INT1 */
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#define SURFBOARDINT_QDMA2_INT2 QDMA_WAN2_INTR /* QDMA2, INT2 */
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#define SURFBOARDINT_QDMA2_INT3 QDMA_WAN3_INTR /* QDMA2, INT3 */
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#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
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#define SURFBOARDINT_UART2 SURFBOARDINT_UART_LITE2
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#define SURFBOARDINT_END (INTR_SOURCES_NUM - 1)
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#elif defined(CONFIG_MIPS_TC3262_34K)
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#define SURFBOARDINT_UART1 UART_INT /* UART1 */
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#define SURFBOARDINT_GPIO GPIO_INT /* GPIO */
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#define SURFBOARDINT_PCM PCM1_INT /* PCM1 */
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#define SURFBOARDINT_DMA APB_DMA0_INT /* DMA */
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#define SURFBOARDINT_ESW ESW_INT /* ESW */
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#define SURFBOARDINT_USB IRQ_RT3XXX_USB /* USB */
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#define SURFBOARDINT_FE FE_MAC_INT /* Frame Engine */
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#define SURFBOARDINT_QDMA SAR_INT /* QDMA */
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#define SURFBOARDINT_PCIE0 PCIE_0_INT /* PCIe0 */
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#define SURFBOARDINT_PCIE1 PCIE_A_INT /* PCIe1 */
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#define SURFBOARDINT_CRYPTO CRYPTO_INT /* CryptoEngine */
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#define SURFBOARDINT_END 40 /* 1 offset + 40 TC */
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#endif
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#endif
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