116 lines
3.7 KiB
C
116 lines
3.7 KiB
C
#ifndef __ASM_MACH_MIPS_TC3262_RT_MMAP_H
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#define __ASM_MACH_MIPS_TC3262_RT_MMAP_H
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/* EN7512(3)/EN7516/EN7527/EN7528 */
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#define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
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#define sysRegRead(phys) (*(volatile unsigned int *)PHYS_TO_K1(phys))
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#define sysRegWrite(phys, val) ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val))
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#define RALINK_SYSCTL_BASE 0xBFB00000
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#define RALINK_TIMER_BASE 0xBFBF0100
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#define RALINK_MEMCTRL_BASE 0xBFB20000
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#define RALINK_PIO_BASE 0xBFBF0200
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#define RALINK_I2C_BASE 0xBFBF8000
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#define RALINK_UART_LITE_BASE 0xBFBF0000
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#define RALINK_UART_LITE2_BASE 0xBFBF0300
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#define RALINK_PCM_BASE 0xBFBD0000
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#define RALINK_GDMA_BASE 0xBFB30000
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#define RALINK_FRAME_ENGINE_BASE 0xBFB50000
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#define RALINK_ETH_SW_BASE 0xBFB58000
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#define RALINK_CRYPTO_ENGINE_BASE 0xBFB70000
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#define RALINK_PCI_BASE 0xBFB80000
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#define RALINK_PCI_PHY0_BASE 0xBFAF2000
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#define RALINK_PCI_PHY1_BASE 0xBFAC0000
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#define RALINK_USB_HOST_BASE 0x1FB90000
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#define RALINK_XHCI_HOST_BASE 0xBFB90000
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#define RALINK_XHCI_UPHY_BASE 0xBFA80000
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#define RALINK_SFC_BASE 0xBFA10000
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#define RALINK_CHIP_SCU_BASE 0xBFA20000
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#define RALINK_11N_MAC_BASE 0xBFB00000 // Unused
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#if defined(CONFIG_ECONET_EN7528)
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#define RALINK_USB_HOST_SIZE 0x00003E00
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#define RALINK_USB_IPPC_BASE 0x1FB93E00
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#define RALINK_USB_UPHY_P0_BASE (RALINK_XHCI_UPHY_BASE + 0x0300)
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#define RALINK_USB_UPHY_P1_BASE (RALINK_XHCI_UPHY_BASE + 0x1300)
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#else
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#define RALINK_USB_HOST_SIZE 0x00004000
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#define RALINK_USB_IPPC_BASE 0x1FA80700
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#define RALINK_USB_UPHY_P0_BASE (RALINK_XHCI_UPHY_BASE + 0x0800)
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#define RALINK_USB_UPHY_P1_BASE (RALINK_XHCI_UPHY_BASE + 0x1000)
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#endif
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#if defined(CONFIG_ECONET_EN7528)
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#define RALINK_WOE0_BASE 0x1FA02000
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#define RALINK_WOE1_BASE 0x1FA03000
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#define RALINK_WDMA0_BASE 0x1FA06000
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#define RALINK_WDMA1_BASE 0x1FA06400
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#endif
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#ifdef CONFIG_MIPS_TC3262_1004K
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/* GIC */
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#define RALINK_GIC_BASE 0x1F8C0000
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#define RALINK_GIC_ADDRSPACE_SZ 0x20000
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/* CPC */
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#define RALINK_CPC_BASE 0x1F8E8000
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#define RALINK_CPC_ADDRSPACE_SZ 0x8000
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/* GCMP */
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#define RALINK_GCMP_BASE 0x1F8E0000
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#define RALINK_GCMP_ADDRSPACE_SZ 0x8000
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/* CM */
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#define CM_GCR_REG0_BASE_VALUE 0x1C000000 /* CM region 0 base address (Palmbus) */
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#define CM_GCR_REG0_MASK_VALUE 0x0000FC00 /* CM region 0 mask (64M) */
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#define CM_GCR_REG1_BASE_VALUE 0x20000000 /* CM region 1 base address (PCIe) */
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#define CM_GCR_REG1_MASK_VALUE 0x0000F000 /* CM region 1 mask (256M) */
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#else
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/* Interrupt Controller */
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#define RALINK_INTCL_BASE 0xBFB40000
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#define RALINK_INTCTL_UARTLITE (1<<0)
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#define RALINK_INTCTL_PIO (1<<10)
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#define RALINK_INTCTL_PCM (1<<11)
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#define RALINK_INTCTL_DMA (1<<14)
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#define RALINK_INTCTL_GSW (1<<15)
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#define RALINK_INTCTL_UHST (1<<17)
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#define RALINK_INTCTL_FE (1<<21)
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#define RALINK_INTCTL_QDMA (1<<22)
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#define RALINK_INTCTL_PCIE0 (1<<23)
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#define RALINK_INTCTL_PCIE1 (1<<24)
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/* Reset Control Register */
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#define RALINK_INTC_RST (1<<9)
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#endif
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/* Reset Control Register */
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#define RALINK_I2S1_RST (1<<0)
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#define RALINK_FE_QDMA_LAN_RST (1<<1)
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#define RALINK_FE_QDMA_WAN_RST (1<<2)
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#define RALINK_PCM2_RST (1<<4)
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#define RALINK_PTM_MAC_RST (1<<5)
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#define RALINK_CRYPTO_RST (1<<6)
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#define RALINK_SAR_RST (1<<7)
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#define RALINK_TIMER_RST (1<<8)
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#define RALINK_BONDING_RST (1<<10)
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#define RALINK_PCM1_RST (1<<11)
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#define RALINK_UART_RST (1<<12)
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#define RALINK_PIO_RST (1<<13)
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#define RALINK_DMA_RST (1<<14)
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#define RALINK_I2C_RST (1<<16)
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#define RALINK_I2S2_RST (1<<17)
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#define RALINK_SPI_RST (1<<18)
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#define RALINK_UARTL_RST (1<<19)
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#define RALINK_FE_RST (1<<21)
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#define RALINK_UHST_RST (1<<22)
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#define RALINK_ESW_RST (1<<23)
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#define RALINK_SFC2_RST (1<<25)
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#define RALINK_PCIE0_RST (1<<26)
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#define RALINK_PCIE1_RST (1<<27)
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#define RALINK_PCIEHB_RST (1<<29)
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#endif
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