43 lines
952 B
C
43 lines
952 B
C
/*
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*
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*/
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#ifndef _ASSEMBLER_
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struct cpulaunch {
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unsigned long pc;
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unsigned long gp;
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unsigned long sp;
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unsigned long a0;
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unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */
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unsigned long flags;
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};
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#else
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#define LOG2CPULAUNCH 5
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#define LAUNCH_PC 0
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#define LAUNCH_GP 4
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#define LAUNCH_SP 8
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#define LAUNCH_A0 12
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#define LAUNCH_FLAGS 28
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#endif
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#define LAUNCH_FREADY 1
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#define LAUNCH_FGO 2
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#define LAUNCH_FGONE 4
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#define CPULAUNCH 0x00000f00
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#define NCPULAUNCH 8
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/* Polling period in count cycles for secondary CPU's */
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#define LAUNCHPERIOD 10000
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/* use GDMP SRAM for CPU 1,2,3's waiting code and launch flags */
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#define GDMP_SRAM_BASE 0xBFA40000
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#define BUSY_WAIT_ZONE_START 0x040
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#define BUSY_WAIT_ZONE_SIZE 0x100
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#define BUSY_WAIT_ZONE_BASE (GDMP_SRAM_BASE + BUSY_WAIT_ZONE_START) /* 0xbfa40040 */
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#define CPU_LAUNCH_BASE (GDMP_SRAM_BASE + BUSY_WAIT_ZONE_START + BUSY_WAIT_ZONE_SIZE) /* 0xbfa40140 */
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