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kernel-49/arch/mips/include/asm/tc3162/cpu-feature-overrides.h
2019-06-24 23:08:51 +03:00

87 lines
2.1 KiB
C

/*
* Ralink specific CPU feature overrides
*
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef __ASM_MACH_MIPS_TC3262_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_MIPS_TC3262_CPU_FEATURE_OVERRIDES_H
/* EN75xx */
/* CPU options */
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_nofpuex 0
#define cpu_has_llsc 1
#define cpu_has_inclusive_pcaches 0
#define cpu_has_prefetch 1
#define cpu_has_vint 1
#define cpu_has_veic 1
#define cpu_has_userlocal 1
#define cpu_has_perf_cntr_intr_bit 1
#define cpu_has_rixi 0
/* CPU ases */
#define cpu_has_mips16 1
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_dsp 1
#define cpu_has_mipsmt 1
#define cpu_has_dsp2 0
#define cpu_has_vz 0
/* CPU ISA level */
#define cpu_has_mips_2 1
#define cpu_has_mips_3 0
#define cpu_has_mips_4 0
#define cpu_has_mips_5 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_mips32r6 0
#define cpu_has_mips64r6 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
/* CPU cache info */
#define cpu_has_vtag_icache 0
#define cpu_has_ic_fills_f_dc 0
#ifdef CONFIG_MIPS_TC3262_1004K
#define cpu_has_dc_aliases 0
#else
#define cpu_icache_snoops_remote_store 1
#define cpu_has_dc_aliases 1
#endif
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#endif