209 lines
10 KiB
C
209 lines
10 KiB
C
/*
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* Copyright (C) 2001 Palmchip Corporation. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Defines for the Surfboard interrupt controller.
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*
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*/
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#ifndef __ASM_MACH_MIPS_RT2880_SURFBOARDINT_H
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#define __ASM_MACH_MIPS_RT2880_SURFBOARDINT_H
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#if defined(CONFIG_RALINK_MT7621)
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#ifdef CONFIG_MIPS_GIC
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#include <linux/irqchip/mips-gic.h>
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#else
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#define GIC_NUM_LOCAL_INTRS 7
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#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
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#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
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#endif
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/* MIPS GIC controller */
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#define GIC_NUM_INTRS 64
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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#define SURFBOARDINT_FE (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(3)) /* FE */
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#define SURFBOARDINT_PCIE0 (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(4)) /* PCIE0 */
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#define SURFBOARDINT_AUX_TIMER (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(5)) /* AUX timer (systick) */
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#define SURFBOARDINT_SYSCTL (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(6)) /* SYSCTL */
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#define SURFBOARDINT_I2C (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(8)) /* I2C */
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#define SURFBOARDINT_DRAMC (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(9)) /* DRAMC */
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#define SURFBOARDINT_PCM (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(10)) /* PCM */
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#define SURFBOARDINT_HSGDMA (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(11)) /* HSGDMA */
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#define SURFBOARDINT_GPIO (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(12)) /* GPIO */
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#define SURFBOARDINT_DMA (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(13)) /* GDMA */
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#define SURFBOARDINT_NAND (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(14)) /* NAND */
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#define SURFBOARDINT_NAND_ECC (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(15)) /* NFI ECC */
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#define SURFBOARDINT_I2S (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(16)) /* I2S */
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#define SURFBOARDINT_SPI (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(17)) /* SPI */
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#define SURFBOARDINT_SPDIF (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(18)) /* SPDIF */
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#define SURFBOARDINT_CRYPTO (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(19)) /* CryptoEngine */
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#define SURFBOARDINT_SDXC (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(20)) /* SDXC */
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#define SURFBOARDINT_R2P (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(21)) /* Rbus to Pbus */
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#define SURFBOARDINT_USB (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(22)) /* USB */
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#define SURFBOARDINT_ESW (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(23)) /* Switch */
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#define SURFBOARDINT_PCIE1 (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(24)) /* PCIE1 */
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#define SURFBOARDINT_PCIE2 (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(25)) /* PCIE2 */
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#define SURFBOARDINT_UART_LITE1 (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(26)) /* UART Lite */
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#define SURFBOARDINT_UART_LITE2 (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(27)) /* UART Lite */
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#define SURFBOARDINT_UART_LITE3 (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(28)) /* UART Lite */
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#define SURFBOARDINT_WDG (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(29)) /* WDG timer */
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#define SURFBOARDINT_TIMER0 (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(30)) /* Timer0 */
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#define SURFBOARDINT_TIMER1 (MIPS_GIC_IRQ_BASE + GIC_SHARED_TO_HWIRQ(31)) /* Timer1 */
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#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
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#define SURFBOARDINT_UART2 SURFBOARDINT_UART_LITE2
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#define SURFBOARDINT_END (MIPS_GIC_IRQ_BASE + GIC_NUM_LOCAL_INTRS + GIC_NUM_INTRS - 1)
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#elif defined(CONFIG_RALINK_MT7628)
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#define MIPS_INTC_CHAIN_HW0 (MIPS_CPU_IRQ_BASE + 2) /* Chain IP2 */
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#define MIPS_INTC_CHAIN_HW1 (MIPS_CPU_IRQ_BASE + 3) /* Chain IP3 */
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#define SURFBOARDINT_PCIE0 (MIPS_CPU_IRQ_BASE + 4) /* PCIe Slot0 */
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#define SURFBOARDINT_FE (MIPS_CPU_IRQ_BASE + 5) /* Frame Engine */
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#define SURFBOARDINT_WLAN (MIPS_CPU_IRQ_BASE + 6) /* Wireless */
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#define SURFBOARDINT_MIPS_TIMER (MIPS_CPU_IRQ_BASE + 7) /* MIPS Timer */
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#define INTC_NUM_INTRS 32
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#define MIPS_INTC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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#define SURFBOARDINT_SYSCTL (MIPS_INTC_IRQ_BASE + 0) /* SYSCTL */
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#define SURFBOARDINT_ILL_ACC (MIPS_INTC_IRQ_BASE + 3) /* Illegal access */
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#define SURFBOARDINT_PCM (MIPS_INTC_IRQ_BASE + 4) /* PCM */
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#define SURFBOARDINT_GPIO (MIPS_INTC_IRQ_BASE + 6) /* GPIO */
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#define SURFBOARDINT_DMA (MIPS_INTC_IRQ_BASE + 7) /* DMA */
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#define SURFBOARDINT_NAND (MIPS_INTC_IRQ_BASE + 8) /* NAND */
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#define SURFBOARDINT_PCTRL (MIPS_INTC_IRQ_BASE + 9) /* Performance counter */
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#define SURFBOARDINT_I2S (MIPS_INTC_IRQ_BASE + 10) /* I2S */
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#define SURFBOARDINT_SPI (MIPS_INTC_IRQ_BASE + 11) /* SPI */
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#define SURFBOARDINT_SDXC (MIPS_INTC_IRQ_BASE + 14) /* SDXC */
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#define SURFBOARDINT_R2P (MIPS_INTC_IRQ_BASE + 15) /* Rbus to Pbus */
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#define SURFBOARDINT_AESENGINE (MIPS_INTC_IRQ_BASE + 13) /* AES Engine */
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#define SURFBOARDINT_UART_LITE1 (MIPS_INTC_IRQ_BASE + 20) /* UART Lite 1 */
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#define SURFBOARDINT_UART_LITE2 (MIPS_INTC_IRQ_BASE + 21) /* UART Lite 2 */
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#define SURFBOARDINT_UART_LITE3 (MIPS_INTC_IRQ_BASE + 22) /* UART Lite 3 */
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#define SURFBOARDINT_WDG (MIPS_INTC_IRQ_BASE + 23) /* WDG timer */
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#define SURFBOARDINT_TIMER0 (MIPS_INTC_IRQ_BASE + 24) /* Timer0 */
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#define SURFBOARDINT_TIMER1 (MIPS_INTC_IRQ_BASE + 25) /* Timer1 */
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#define SURFBOARDINT_PWM (MIPS_INTC_IRQ_BASE + 26) /* PWM */
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#define SURFBOARDINT_WWAKE (MIPS_INTC_IRQ_BASE + 27) /* WLAN Wake */
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#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
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#define SURFBOARDINT_UART2 SURFBOARDINT_UART_LITE2
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#define SURFBOARDINT_ESW (MIPS_INTC_IRQ_BASE + 17) /* Embedded Switch */
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#define SURFBOARDINT_UHST (MIPS_INTC_IRQ_BASE + 18) /* USB Host */
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#define SURFBOARDINT_UDEV (MIPS_INTC_IRQ_BASE + 19) /* USB Device */
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#define SURFBOARDINT_END (MIPS_INTC_IRQ_BASE + INTC_NUM_INTRS - 1)
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#elif defined(CONFIG_MIPS_TC3262_1004K)
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#include <asm/tc3162/tc3262_int_source.h>
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/* MIPS GIC controller (via EIC) */
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#define GIC_NUM_INTRS 64
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0)
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#define SURFBOARDINT_UART_LITE1 UART_INT /* UART Lite1 */
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#define SURFBOARDINT_TIMER0 TIMER0_INT, /* Timer0 */
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#define SURFBOARDINT_TIMER1 TIMER1_INT /* Timer1 */
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#define SURFBOARDINT_TIMER2 TIMER2_INT /* Timer2 */
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#define SURFBOARDINT_WDG TIMER5_INT /* WDG timer */
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#define SURFBOARDINT_GPIO GPIO_INT /* GPIO */
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#define SURFBOARDINT_PCM PCM1_INT /* PCM */
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#define SURFBOARDINT_ESW MAC1_INT /* ESW */
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#define SURFBOARDINT_UART_LITE2 UART2_INT /* UART Lite2 */
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#define SURFBOARDINT_USB IRQ_RT3XXX_USB /* USB */
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#define SURFBOARDINT_DMT DMT_INT /* xDSL DMT */
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#define SURFBOARDINT_QDMA1 QDMA_LAN0_INTR /* QDMA1, INT0 */
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#define SURFBOARDINT_QDMA2 QDMA_WAN0_INTR /* QDMA2, INT0 */
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#define SURFBOARDINT_PCIE0 PCIE_0_INT /* PCIE0 */
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#define SURFBOARDINT_PCIE1 PCIE_A_INT /* PCIE1 */
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#define SURFBOARDINT_CRYPTO CRYPTO_INT /* CryptoEngine */
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#define SURFBOARDINT_QDMA1_INT1 QDMA_LAN1_INTR /* QDMA1, INT1 */
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#define SURFBOARDINT_QDMA1_INT2 QDMA_LAN2_INTR /* QDMA1, INT2 */
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#define SURFBOARDINT_QDMA1_INT3 QDMA_LAN3_INTR /* QDMA1, INT3 */
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#define SURFBOARDINT_QDMA2_INT1 QDMA_WAN1_INTR /* QDMA2, INT1 */
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#define SURFBOARDINT_QDMA2_INT2 QDMA_WAN2_INTR /* QDMA2, INT2 */
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#define SURFBOARDINT_QDMA2_INT3 QDMA_WAN3_INTR /* QDMA2, INT3 */
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#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
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#define SURFBOARDINT_UART2 SURFBOARDINT_UART_LITE2
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#define SURFBOARDINT_END (INTR_SOURCES_NUM - 1)
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#elif defined(CONFIG_MIPS_TC3262_34K)
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#include <asm/tc3162/tc3262_int_source.h>
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#define SURFBOARDINT_UART1 UART_INT /* UART1 */
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#define SURFBOARDINT_GPIO GPIO_INT /* GPIO */
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#define SURFBOARDINT_PCM PCM1_INT /* PCM1 */
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#define SURFBOARDINT_DMA APB_DMA0_INT /* DMA */
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#define SURFBOARDINT_ESW ESW_INT /* ESW */
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#define SURFBOARDINT_USB IRQ_RT3XXX_USB /* USB */
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#define SURFBOARDINT_FE FE_MAC_INT /* Frame Engine */
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#define SURFBOARDINT_QDMA SAR_INT /* QDMA */
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#define SURFBOARDINT_PCIE0 PCIE_0_INT /* PCIe0 */
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#define SURFBOARDINT_PCIE1 PCIE_A_INT /* PCIe1 */
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#define SURFBOARDINT_CRYPTO CRYPTO_INT /* CryptoEngine */
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#define SURFBOARDINT_END 40 /* 1 offset + 40 TC */
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#else
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#error "Ralink chip undefined for INT map"
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#endif
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/*
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* Surfboard registers are memory mapped on 32-bit aligned boundaries and
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* only word access are allowed.
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*/
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#ifndef CONFIG_MIPS_TC3262
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#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT
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#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT
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#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL
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#define RALINK_INTRAW (RALINK_INTCL_BASE + 0xA4) //INT_PURE
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#define RALINK_INTENA (RALINK_INTCL_BASE + 0x80) //IRQ_MASK_SET
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#define RALINK_FIQENA (RALINK_INTCL_BASE + 0x84) //FIQ_MASK_SET
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#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x78) //IRQ_MASK_CLR
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#define RALINK_FIQDIS (RALINK_INTCL_BASE + 0x7C) //FIQ_MASK_CLR
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#endif
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/* bobtseng added ++, 2006.3.6. */
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#define read_32bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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"mfc0\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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__res;})
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#define write_32bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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"mtc0\t%0,"STR(register)"\n\t" \
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"nop" \
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: : "r" (value));
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/* bobtseng added --, 2006.3.6. */
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#endif
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