43e137091b
Changes in 4.9.310 arm64: errata: Provide macro for major and minor cpu revisions arm64: Remove useless UAO IPI and describe how this gets enabled arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35 arm64: capabilities: Update prototype for enable call back arm64: capabilities: Move errata work around check on boot CPU arm64: capabilities: Move errata processing code arm64: capabilities: Prepare for fine grained capabilities arm64: capabilities: Add flags to handle the conflicts on late CPU arm64: capabilities: Clean up midr range helpers arm64: Add helpers for checking CPU MIDR against a range arm64: capabilities: Add support for checks based on a list of MIDRs clocksource/drivers/arm_arch_timer: Remove fsl-a008585 parameter clocksource/drivers/arm_arch_timer: Introduce generic errata handling infrastructure arm64: arch_timer: Add infrastructure for multiple erratum detection methods arm64: arch_timer: Add erratum handler for CPU-specific capability arm64: arch_timer: Add workaround for ARM erratum 1188873 arm64: arch_timer: avoid unused function warning arm64: Add silicon-errata.txt entry for ARM erratum 1188873 arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT arm64: Add part number for Neoverse N1 arm64: Add part number for Arm Cortex-A77 arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: Add Cortex-X2 CPU part definition arm64: Add helper to decode register from instruction arm64: entry.S: Add ventry overflow sanity checks arm64: entry: Make the trampoline cleanup optional arm64: entry: Free up another register on kpti's tramp_exit path arm64: entry: Move the trampoline data page before the text page arm64: entry: Allow tramp_alias to access symbols after the 4K boundary arm64: entry: Don't assume tramp_vectors is the start of the vectors arm64: entry: Move trampoline macros out of ifdef'd section arm64: entry: Make the kpti trampoline's kpti sequence optional arm64: entry: Allow the trampoline text to occupy multiple pages arm64: entry: Add non-kpti __bp_harden_el1_vectors for mitigations arm64: Move arm64_update_smccc_conduit() out of SSBD ifdef arm64: entry: Add vectors that have the bhb mitigation sequences arm64: entry: Add macro for reading symbol addresses from the trampoline arm64: Add percpu vectors for EL1 KVM: arm64: Add templates for BHB mitigation sequences arm64: Mitigate spectre style branch history side channels KVM: arm64: Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migrated arm64: add ID_AA64ISAR2_EL1 sys register arm64: Use the clearbhb instruction in mitigations Linux 4.9.310 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I689d7634aebe9d9ffba8d72d1d76bb237ca228a4
131 lines
2.9 KiB
ArmAsm
131 lines
2.9 KiB
ArmAsm
/*
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* Contains CPU specific branch predictor invalidation sequences
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*
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* Copyright (C) 2018 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/arm-smccc.h>
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.macro ventry target
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.rept 31
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nop
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.endr
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b \target
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.endm
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.macro vectors target
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ventry \target + 0x000
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ventry \target + 0x080
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ventry \target + 0x100
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ventry \target + 0x180
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ventry \target + 0x200
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ventry \target + 0x280
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ventry \target + 0x300
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ventry \target + 0x380
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ventry \target + 0x400
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ventry \target + 0x480
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ventry \target + 0x500
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ventry \target + 0x580
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ventry \target + 0x600
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ventry \target + 0x680
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ventry \target + 0x700
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ventry \target + 0x780
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.endm
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.align 11
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ENTRY(__bp_harden_hyp_vecs_start)
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.rept 4
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vectors __kvm_hyp_vector
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.endr
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ENTRY(__bp_harden_hyp_vecs_end)
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.macro smccc_workaround_1 inst
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sub sp, sp, #(8 * 4)
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stp x2, x3, [sp, #(8 * 0)]
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stp x0, x1, [sp, #(8 * 2)]
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mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1
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\inst #0
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ldp x2, x3, [sp, #(8 * 0)]
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ldp x0, x1, [sp, #(8 * 2)]
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add sp, sp, #(8 * 4)
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.endm
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ENTRY(__smccc_workaround_1_smc_start)
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smccc_workaround_1 smc
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ENTRY(__smccc_workaround_1_smc_end)
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ENTRY(__smccc_workaround_1_hvc_start)
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smccc_workaround_1 hvc
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ENTRY(__smccc_workaround_1_hvc_end)
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ENTRY(__smccc_workaround_3_smc_start)
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sub sp, sp, #(8 * 4)
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stp x2, x3, [sp, #(8 * 0)]
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stp x0, x1, [sp, #(8 * 2)]
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mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3
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smc #0
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ldp x2, x3, [sp, #(8 * 0)]
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ldp x0, x1, [sp, #(8 * 2)]
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add sp, sp, #(8 * 4)
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ENTRY(__smccc_workaround_3_smc_end)
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ENTRY(__spectre_bhb_loop_k8_start)
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sub sp, sp, #(8 * 2)
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stp x0, x1, [sp, #(8 * 0)]
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mov x0, #8
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2: b . + 4
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subs x0, x0, #1
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b.ne 2b
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dsb nsh
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isb
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ldp x0, x1, [sp, #(8 * 0)]
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add sp, sp, #(8 * 2)
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ENTRY(__spectre_bhb_loop_k8_end)
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ENTRY(__spectre_bhb_loop_k24_start)
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sub sp, sp, #(8 * 2)
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stp x0, x1, [sp, #(8 * 0)]
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mov x0, #24
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2: b . + 4
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subs x0, x0, #1
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b.ne 2b
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dsb nsh
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isb
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ldp x0, x1, [sp, #(8 * 0)]
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add sp, sp, #(8 * 2)
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ENTRY(__spectre_bhb_loop_k24_end)
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ENTRY(__spectre_bhb_loop_k32_start)
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sub sp, sp, #(8 * 2)
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stp x0, x1, [sp, #(8 * 0)]
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mov x0, #32
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2: b . + 4
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subs x0, x0, #1
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b.ne 2b
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dsb nsh
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isb
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ldp x0, x1, [sp, #(8 * 0)]
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add sp, sp, #(8 * 2)
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ENTRY(__spectre_bhb_loop_k32_end)
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ENTRY(__spectre_bhb_clearbhb_start)
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hint #22 /* aka clearbhb */
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isb
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ENTRY(__spectre_bhb_clearbhb_end)
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