668 lines
18 KiB
Plaintext
668 lines
18 KiB
Plaintext
/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7981-clk.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "mediatek,mt7981";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clk40m: oscillator-40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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clock-output-names = "clkxtal";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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next-level-cache = <&L2_CA53>;
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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next-level-cache = <&L2_CA53>;
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reg = <0x1>;
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};
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L2_CA53: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x30000>;
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no-map;
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};
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wmcpu_emi: wmcpu-reserved@47c80000 {
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compatible = "mediatek,wmcpu-reserved";
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no-map;
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reg = <0 0x47c80000 0 0x00100000>;
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};
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wocpu0_emi: wocpu0_emi@47d80000 {
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compatible = "mediatek,wocpu0_emi";
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no-map;
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reg = <0 0x47d80000 0 0x40000>;
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shared = <0>;
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};
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wocpu_data: wocpu_data@47dc0000 {
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compatible = "mediatek,wocpu_data";
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no-map;
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reg = <0 0x47dc0000 0 0x240000>;
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shared = <1>;
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};
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};
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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clock-frequency = <13000000>;
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};
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infracfg_ao: infracfg_ao@10001000 {
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compatible = "mediatek,mt7981-infracfg_ao", "syscon";
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reg = <0 0x10001000 0 0x68>;
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#clock-cells = <1>;
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};
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infracfg: infracfg@10001040 {
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compatible = "mediatek,mt7981-infracfg", "syscon";
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reg = <0 0x10001068 0 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: topckgen@1001b000 {
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compatible = "mediatek,mt7981-topckgen", "syscon";
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reg = <0 0x1001b000 0 0x1000>;
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#clock-cells = <1>;
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};
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apmixedsys: apmixedsys@1001e000 {
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compatible = "mediatek,mt7981-apmixedsys", "syscon";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&thermal 0>;
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};
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};
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thermal: thermal@1100c800 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt7981-thermal";
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reg = <0 0x1100c800 0 0x800>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_THERM_CK>,
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<&infracfg_ao CK_INFRA_ADC_26M_CK>,
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<&infracfg_ao CK_INFRA_ADC_FRC_CK>;
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clock-names = "therm", "auxadc", "adc_32k";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration>;
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nvmem-cell-names = "calibration-data";
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};
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auxadc: adc@1100d000 {
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compatible = "mediatek,mt7981-auxadc",
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"mediatek,mt7622-auxadc";
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reg = <0 0x1100d000 0 0x1000>;
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clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>,
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<&infracfg_ao CK_INFRA_ADC_FRC_CK>;
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clock-names = "main", "32k";
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#io-channel-cells = <1>;
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};
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7981-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&infracfg_ao CK_INFRA_PWM_STA>,
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<&infracfg_ao CK_INFRA_PWM_HCK>,
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<&infracfg_ao CK_INFRA_PWM1_CK>,
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<&infracfg_ao CK_INFRA_PWM2_CK>,
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<&infracfg_ao CK_INFRA_PWM3_CK>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
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};
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wed_pcie: wed_pcie@10003000 {
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compatible = "mediatek,wed_pcie";
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reg = <0 0x10003000 0 0x10>;
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};
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wed: wed@15010000 {
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compatible = "mediatek,wed";
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wed_num = <2>;
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pci_slot_map = <0>, <1>;
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reg = <0 0x15010000 0 0x1000>,
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<0 0x15011000 0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
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};
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wdma: wdma@15104800 {
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compatible = "mediatek,wed-wdma";
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reg = <0 0x15104800 0 0x400>,
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<0 0x15104c00 0 0x400>;
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};
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ap2woccif: ap2woccif@151A5000 {
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compatible = "mediatek,ap2woccif";
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reg = <0 0x151a5000 0 0x1000>,
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<0 0x151ad000 0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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};
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wocpu0_ilm: wocpu0_ilm@151e0000 {
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compatible = "mediatek,wocpu0_ilm";
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reg = <0 0x151e0000 0 0x8000>;
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};
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wocpu_dlm: wocpu_dlm@151e8000 {
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compatible = "mediatek,wocpu_dlm";
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reg = <0 0x151e8000 0 0x2000>,
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<0 0x151f8000 0 0x2000>;
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resets = <ðsysrst 0>;
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reset-names = "wocpu_rst";
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};
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cpu_boot: wocpu_boot@15194000 {
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compatible = "mediatek,wocpu_boot";
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reg = <0 0x15194000 0 0x1000>;
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};
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system_clk: dummy_system_clk {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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};
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gpt_timer: timer@10008000 {
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compatible = "mediatek,mt7986-timer";
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reg = <0 0x10008000 0 0x1000>;
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interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&system_clk>;
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clock-names = "system-clk";
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7986-wdt";
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reg = <0 0x1001c000 0 0x1000>;
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timeout-sec = <30>;
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mediatek,timer = <&gpt_timer>;
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#reset-cells = <1>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART0_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART1_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART2_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt7981-i2c";
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reg = <0 0x11007000 0 0x1000>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <1>;
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clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
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<&infracfg_ao CK_INFRA_AP_DMA_CK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pcie: pcie@11280000 {
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compatible = "mediatek,mt7986-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11280000 0 0x4000>;
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reg-names = "pcie-mac";
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000
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0x0 0x20000000 0 0x10000000>;
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clocks = <&infracfg_ao CK_INFRA_IPCIE_PIPE_CK>,
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<&infracfg_ao CK_INFRA_IPCIE_CK>,
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<&infracfg_ao CK_INFRA_IPCIER_CK>,
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<&infracfg_ao CK_INFRA_IPCIEB_CK>;
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clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
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status = "disabled";
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phys = <&u3port0 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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pcie_intc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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crypto: crypto@10320000 {
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compatible = "inside-secure,safexcel-eip97";
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reg = <0 0x10320000 0 0x40000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ring0", "ring1", "ring2", "ring3";
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clocks = <&topckgen CK_TOP_EIP97B>;
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clock-names = "top_eip97_ck";
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assigned-clocks = <&topckgen CK_TOP_EIP97B_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_NET1_D5>;
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};
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trng: rng-arm-smccc {
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compatible = "mediatek,mt7981-rng";
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};
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pio: pinctrl@11d00000 {
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compatible = "mediatek,mt7981-pinctrl";
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reg = <0 0x11d00000 0 0x1000>,
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<0 0x11c00000 0 0x1000>,
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<0 0x11c10000 0 0x1000>,
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<0 0x11d20000 0 0x1000>,
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<0 0x11e00000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x11f10000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rt", "iocfg_rm",
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"iocfg_rb", "iocfg_lb", "iocfg_bl",
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"iocfg_tm", "iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 56>;
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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};
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ethsys: syscon@15000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7981-ethsys","syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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ethsysrst: reset-controller {
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compatible = "ti,syscon-reset";
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#reset-cells = <1>;
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ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>;
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};
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
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reg = <0 0x10060000 0 0x1000>;
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pn_swap;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
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reg = <0 0x10070000 0 0x1000>;
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#clock-cells = <1>;
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};
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topmisc: topmisc@11d10000 {
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compatible = "mediatek,mt7981-topmisc", "syscon";
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reg = <0 0x11d10000 0 0x10000>;
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#clock-cells = <1>;
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};
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hnat: hnat@15102200 {
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compatible = "mediatek,mtk-hnat_v4";
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reg = <0 0x15100000 0 0x80000>;
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resets = <ðsys 0>;
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reset-names = "mtketh";
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status = "disabled";
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};
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eth: ethernet@15100000 {
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compatible = "mediatek,mt7981-eth";
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reg = <0 0x15100000 0 0x80000>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <ðsys CK_ETH_FE_EN>,
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<ðsys CK_ETH_GP2_EN>,
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<ðsys CK_ETH_GP1_EN>,
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<ðsys CK_ETH_WOCPU0_EN>,
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<&sgmiisys0 CK_SGM0_TX_EN>,
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<&sgmiisys0 CK_SGM0_RX_EN>,
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<&sgmiisys0 CK_SGM0_CK0_EN>,
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<&sgmiisys0 CK_SGM0_CDR_CK0_EN>,
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<&sgmiisys1 CK_SGM1_TX_EN>,
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<&sgmiisys1 CK_SGM1_RX_EN>,
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<&sgmiisys1 CK_SGM1_CK1_EN>,
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<&sgmiisys1 CK_SGM1_CDR_CK1_EN>;
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clock-names = "fe", "gp2", "gp1", "wocpu0",
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"sgmii_tx250m", "sgmii_rx250m",
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"sgmii_cdr_ref", "sgmii_cdr_fb",
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"sgmii2_tx250m", "sgmii2_rx250m",
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"sgmii2_cdr_ref", "sgmii2_cdr_fb";
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assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
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<&topckgen CK_TOP_SGM_325M_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
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<&topckgen CK_TOP_CB_SGM_325M>;
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
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mediatek,infracfg = <&topmisc>;
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#reset-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wbsys: wbsys@18000000 {
|
|
compatible = "mediatek,wbsys";
|
|
reg = <0 0x18000000 0 0x1000000>;
|
|
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
|
chip_id = <0x7981>;
|
|
};
|
|
|
|
consys: consys@10000000 {
|
|
compatible = "mediatek,mt7981-consys";
|
|
reg = <0 0x10000000 0 0x8600000>;
|
|
memory-region = <&wmcpu_emi>;
|
|
};
|
|
|
|
snand: snfi@11005000 {
|
|
compatible = "mediatek,mt7986-snand";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11005000 0 0x1000>,
|
|
<0 0x11006000 0 0x1000>;
|
|
reg-names = "nfi", "ecc";
|
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
|
|
<&infracfg_ao CK_INFRA_NFI1_CK>,
|
|
<&infracfg_ao CK_INFRA_NFI_HCK_CK>;
|
|
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
|
|
assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
|
|
<&topckgen CK_TOP_NFI1X_SEL>;
|
|
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
|
|
<&topckgen CK_TOP_CB_M_D8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt7986-mmc";
|
|
reg = <0 0x11230000 0 0x1000>,
|
|
<0 0x11c20000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CK_TOP_EMMC_208M>,
|
|
<&topckgen CK_TOP_EMMC_400M>,
|
|
<&infracfg_ao CK_INFRA_MSDC_CK>;
|
|
assigned-clocks = <&topckgen CK_TOP_EMMC_208M_SEL>,
|
|
<&topckgen CK_TOP_EMMC_400M_SEL>;
|
|
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
|
|
<&topckgen CK_TOP_CB_NET2_D2>;
|
|
clock-names = "source", "hclk", "source_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@1100a000 {
|
|
compatible = "mediatek,ipm-spi-quad";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x1100a000 0 0x100>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CK_TOP_CB_M_D2>,
|
|
<&topckgen CK_TOP_SPI_SEL>,
|
|
<&infracfg_ao CK_INFRA_SPI0_CK>,
|
|
<&infracfg_ao CK_INFRA_SPI0_HCK_CK>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@1100b000 {
|
|
compatible = "mediatek,ipm-spi-single";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x1100b000 0 0x100>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CK_TOP_CB_M_D2>,
|
|
<&topckgen CK_TOP_SPIM_MST_SEL>,
|
|
<&infracfg_ao CK_INFRA_SPI1_CK>,
|
|
<&infracfg_ao CK_INFRA_SPI1_HCK_CK>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@11009000 {
|
|
compatible = "mediatek,ipm-spi-quad";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11009000 0 0x100>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CK_TOP_CB_M_D2>,
|
|
<&topckgen CK_TOP_SPI_SEL>,
|
|
<&infracfg_ao CK_INFRA_SPI2_CK>,
|
|
<&infracfg_ao CK_INFRA_SPI2_HCK_CK>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
xhci: xhci@11200000 {
|
|
compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0 0x11200000 0 0x2e00>,
|
|
<0 0x11203e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CK_TOP_U2U3_XHCI_SEL>,
|
|
<&infracfg_ao CK_INFRA_IUSB_SYS_CK>,
|
|
<&infracfg_ao CK_INFRA_IUSB_CK>,
|
|
<&infracfg_ao CK_INFRA_IUSB_133_CK>,
|
|
<&infracfg_ao CK_INFRA_IUSB_66M_CK>;
|
|
clock-names = "xhci_ck", "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
|
|
phys = <&u2port0 PHY_TYPE_USB2>;
|
|
mediatek,u3p-dis-msk = <0x01>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_phy: t-phy-shared {
|
|
compatible = "mediatek,generic-tphy-v2";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
u2port0: usb-phy@11e10000 {
|
|
reg = <0 0x11e10000 0 0x700>;
|
|
clocks = <&system_clk>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
u3port0: usb-phy@11e10700 {
|
|
reg = <0 0x11e10700 0 0x900>;
|
|
clocks = <&system_clk>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
mediatek,syscon-type = <&topmisc 0x218 0>;
|
|
nvmem-cells = <&comb_intr_p0>,
|
|
<&comb_rx_imp_p0>,
|
|
<&comb_tx_imp_p0>;
|
|
nvmem-cell-names = "intr", "rx_imp", "tx_imp";
|
|
};
|
|
};
|
|
|
|
afe: audio-controller@11210000 {
|
|
compatible = "mediatek,mt79xx-audio";
|
|
reg = <0 0x11210000 0 0x9000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>,
|
|
<&infracfg_ao CK_INFRA_AUD_26M_CK>,
|
|
<&infracfg_ao CK_INFRA_AUD_L_CK>,
|
|
<&infracfg_ao CK_INFRA_AUD_AUD_CK>,
|
|
<&infracfg_ao CK_INFRA_AUD_EG2_CK>,
|
|
<&topckgen CK_TOP_AUD_SEL>;
|
|
clock-names = "aud_bus_ck",
|
|
"aud_26m_ck",
|
|
"aud_l_ck",
|
|
"aud_aud_ck",
|
|
"aud_eg2_ck",
|
|
"aud_sel";
|
|
assigned-clocks = <&topckgen CK_TOP_AUD_SEL>,
|
|
<&topckgen CK_TOP_A1SYS_SEL>,
|
|
<&topckgen CK_TOP_AUD_L_SEL>,
|
|
<&topckgen CK_TOP_A_TUNER_SEL>;
|
|
assigned-clock-parents = <&topckgen CK_TOP_CB_APLL2_196M>,
|
|
<&topckgen CK_TOP_APLL2_D4>,
|
|
<&topckgen CK_TOP_CB_APLL2_196M>,
|
|
<&topckgen CK_TOP_APLL2_D4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
efuse: efuse@11f20000 {
|
|
compatible = "mediatek,efuse";
|
|
reg = <0 0x11f20000 0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
thermal_calibration: calib@274 {
|
|
reg = <0x274 0xc>;
|
|
};
|
|
|
|
phy_calibration: calib@8dc {
|
|
reg = <0x8dc 0x10>;
|
|
};
|
|
|
|
comb_rx_imp_p0: usb3-rx-imp@8c8 {
|
|
reg = <0x8c8 1>;
|
|
bits = <0 5>;
|
|
};
|
|
|
|
comb_tx_imp_p0: usb3-tx-imp@8c8 {
|
|
reg = <0x8c8 2>;
|
|
bits = <5 5>;
|
|
};
|
|
|
|
comb_intr_p0: usb3-intr@8c9 {
|
|
reg = <0x8c9 1>;
|
|
bits = <2 6>;
|
|
};
|
|
};
|
|
|
|
clkitg: clkitg {
|
|
compatible = "simple-bus";
|
|
};
|
|
|
|
ice: ice_debug {
|
|
compatible = "mediatek,mt2701-ice_debug";
|
|
clocks = <&infracfg_ao CK_INFRA_DBG_CK>;
|
|
clock-names = "ice_dbg";
|
|
};
|
|
};
|
|
|
|
#include "mt7981-clkitg.dtsi"
|