166 lines
7.0 KiB
Diff
166 lines
7.0 KiB
Diff
--- a/drivers/ssb/b43_pci_bridge.c
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+++ b/drivers/ssb/b43_pci_bridge.c
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@@ -29,6 +29,8 @@ static const struct pci_device_id b43_pc
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -228,6 +228,7 @@
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#define SSB_SPROM1_AGAIN_BG_SHIFT 0
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#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
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#define SSB_SPROM1_AGAIN_A_SHIFT 8
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+#define SSB_SPROM1_CCODE 0x0076
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/* SPROM Revision 2 (inherits from rev 1) */
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#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
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@@ -267,6 +268,7 @@
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#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
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/* SPROM Revision 4 */
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+#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
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#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
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#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
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#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
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@@ -389,6 +391,11 @@
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#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
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#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
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#define SSB_SPROM8_GPIOB_P3_SHIFT 8
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+#define SSB_SPROM8_LEDDC 0x009A
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+#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
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+#define SSB_SPROM8_LEDDC_ON_SHIFT 8
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+#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
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+#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
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#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
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#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
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@@ -404,6 +411,13 @@
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#define SSB_SPROM8_AGAIN2_SHIFT 0
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#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
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#define SSB_SPROM8_AGAIN3_SHIFT 8
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+#define SSB_SPROM8_TXRXC 0x00A2
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+#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
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+#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
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+#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
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+#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
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+#define SSB_SPROM8_TXRXC_SWITCH 0xff00
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+#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
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#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
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#define SSB_SPROM8_RSSISMF2G 0x000F
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#define SSB_SPROM8_RSSISMC2G 0x00F0
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@@ -430,6 +444,7 @@
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#define SSB_SPROM8_TRI5GH_SHIFT 8
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#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
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#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
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+#define SSB_SPROM8_RXPO2G_SHIFT 0
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#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
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#define SSB_SPROM8_RXPO5G_SHIFT 8
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#define SSB_SPROM8_FEM2G 0x00AE
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@@ -445,10 +460,38 @@
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#define SSB_SROM8_FEM_ANTSWLUT 0xF800
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#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
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#define SSB_SPROM8_THERMAL 0x00B2
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-#define SSB_SPROM8_MPWR_RAWTS 0x00B4
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-#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
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-#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
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-#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
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+#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
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+#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
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+#define SSB_SPROM8_THERMAL_TRESH 0xff00
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+#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
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+/* Temp sense related entries */
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+#define SSB_SPROM8_RAWTS 0x00B4
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+#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
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+#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
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+#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
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+#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
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+#define SSB_SPROM8_OPT_CORRX 0x00B6
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+#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
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+#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
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+#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
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+#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
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+#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
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+#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
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+/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
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+#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
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+#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
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+#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
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+#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
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+#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
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+#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
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+#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
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+#define SSB_SPROM8_TEMPDELTA 0x00BA
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+#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
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+#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
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+#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
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+#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
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+#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
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+#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
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/* There are 4 blocks with power info sharing the same layout */
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#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
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@@ -482,6 +525,41 @@
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#define SSB_SROM8_5GH_PA_2 0x1C
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/* TODO: Make it deprecated */
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+ #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
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+ #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
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+ #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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+/* There are 4 blocks with power info sharing the same layout */
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+#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
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+#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
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+#define SSB_SROM8_PWR_INFO_CORE2 0x0100
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+#define SSB_SROM8_PWR_INFO_CORE3 0x0120
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+
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+#define SSB_SROM8_2G_MAXP_ITSSI 0x00
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+#define SSB_SPROM8_2G_MAXP 0x00FF
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+#define SSB_SPROM8_2G_ITSSI 0xFF00
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+#define SSB_SPROM8_2G_ITSSI_SHIFT 8
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+#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
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+#define SSB_SROM8_2G_PA_1 0x04
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+#define SSB_SROM8_2G_PA_2 0x06
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+#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
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+#define SSB_SPROM8_5G_MAXP 0x00FF
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+#define SSB_SPROM8_5G_ITSSI 0xFF00
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+#define SSB_SPROM8_5G_ITSSI_SHIFT 8
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+#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
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+#define SSB_SPROM8_5GH_MAXP 0x00FF
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+#define SSB_SPROM8_5GL_MAXP 0xFF00
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+#define SSB_SPROM8_5GL_MAXP_SHIFT 8
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+#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
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+#define SSB_SROM8_5G_PA_1 0x0E
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+#define SSB_SROM8_5G_PA_2 0x10
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+#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
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+#define SSB_SROM8_5GL_PA_1 0x14
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+#define SSB_SROM8_5GL_PA_2 0x16
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+#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
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+#define SSB_SROM8_5GH_PA_1 0x1A
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+#define SSB_SROM8_5GH_PA_2 0x1C
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+
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+/* TODO: Make it deprecated */
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#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
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#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
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#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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@@ -513,6 +591,16 @@
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#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
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#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
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+#define SSB_SPROM8_2G_MCSPO 0x0152
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+#define SSB_SPROM8_5G_MCSPO 0x0162
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+#define SSB_SPROM8_5GL_MCSPO 0x0172
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+#define SSB_SPROM8_5GH_MCSPO 0x0182
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+
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+#define SSB_SPROM8_CDDPO 0x0192
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+#define SSB_SPROM8_STBCPO 0x0194
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+#define SSB_SPROM8_BW40PO 0x0196
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+#define SSB_SPROM8_BWDUPPO 0x0198
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+
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/* Values for boardflags_lo read from SPROM */
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#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
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#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
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