337 lines
13 KiB
C
337 lines
13 KiB
C
/*
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* Copyright (C) 2006 Mindspeed Technologies, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_BOOTDELAY 3
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/*-----------------------------------------------------------------------
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* Comcerto Source Code Configuration
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*/
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#define CONFIG_COMCERTO 1
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#define CONFIG_COMCERTO_1000 1
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#include <asm/hardware.h>
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#define CONFIG_IDENT_STRING " Mindspeed $Name: uboot_7_00_5 $"
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#define CFG_REFCLKFREQ 24000000 /* 24 MHz */
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#define CFG_PHY_CLOCK 125000000 /* 125 MHz*/
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#define CFG_GEM0_CLOCK 25000000 /* 25 MHz*/
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#define CFG_GEM1_CLOCK 25000000 /* 25 MHz*/
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#define CFG_DDR_16BIT 1
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/* DDR Training algorithm */
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#define DDR_TRAINING
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//#undef DDR_TRAINING
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#define DDR_TRAINING_DBG
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/*-----------------------------------------------------------------------
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* Board Configuration
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*/
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#define CONFIG_BOARD_SHG3305 1 /* board */
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/* Linux boot configuration */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define LINUX_BOOTPARAM_ADDR (PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
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/* define one of these to choose the UART0 or UART1 as console */
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#define CONFIG_UART0 1
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#define BOARD_LATE_INIT
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#define MSP_BOTTOM_MEMORY_RESERVED_SIZE 0x800000 /* 8 MiB reserved for MSP */
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#define MSP_TOP_MEMORY_RESERVED_SIZE 0x0 /* 0 MiB reserved for MSP */
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/* NAND GPIOs config */
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#define CFG_NAND_BR_GPIO 6
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#define CFG_NAND_CE_GPIO 29
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#define CFG_NAND_CLE_GPIO 31
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#define CFG_NAND_ALE_GPIO 30
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/* Initial stack configuration */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x0A000000 /* ARAM_BASEADDR Base address */
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#define CONFIG_SYS_INIT_RAM_END 0x00020000 /* 128K */
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#define CFG_ARAM_CODE_SIZE 0x00010000 /* 64K */
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/*-----------------------------------------------------------------------
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* CPU Core Configuration
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*/
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600}
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#define CONFIG_SERVERIP 192.168.1.33
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#define CONFIG_IPADDR 192.168.1.1
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#define CONFIG_ETHADDR 00:aa:bb:cc:dd:ee
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#define CONFIG_VERSION_VARIABLE /* keep u-boot version string in environment */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "Comcerto-1000 > " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Malloc/stack configuration */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
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#endif
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#define CONFIG_SYS_HZ 1000
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/* Memory Mapping */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM DDR_BASEADDR
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#define PHYS_SDRAM_SIZE 0x20000000 /* 512 MB */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM + 0x01000000) /* default load address */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR /* default load address */
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x800000)
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#define CONFIG_LZMA 1
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
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//#define CONFIG_SYS_CONSOLE_INFO_QUIET
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//#define CONFIG_SILENT_CONSOLE
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//#define CONFIG_DISABLE_CONSOLE
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_NAND_BASE EXP_CS4_BASEADDR
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_OFFSET 0x00040000 /* environment starts here */
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#define CONFIG_ENV_SIZE 0x4000
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/* CONFIG_ENV_VERSION
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* v1.0: initial version
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* v1.1: add environment variable 'env_readonly' to set partition 'env' as read-only
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* v1.2: rename environment variable 'env_readonly' to 'readonly' for setting
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* partition 'env' & 'RFData' as read-only
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* v1.3: add environment variable 'zld_ver' to record zloader version and put it in
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* kernel command line
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*/
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#define CONFIG_ENV_VERSION "1.3"
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#define CFG_LOADER_PART_ADDR 0
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#define CFG_LOADER_PART_SIZE 0x40000
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#define CFG_RFDATA_PART_ADDR 0x40000
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#define CFG_RFDATA_PART_SIZE 0x20000
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#define CFG_ROOTFS_PART_ADDR 0x60000
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#define CFG_ROOTFS_PART_SIZE 0xC800000
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#define CFG_ROOTFSDATA_PART_ADDR 0xC860000
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#define CFG_ROOTFSDATA_PART_SIZE 0xC800000
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/*
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* JFFS2 Configuration
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*/
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/* mtdparts command line support */
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nand0=comcertonand"
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#define MTDPARTS_DEFAULT "mtdparts=comcertonand:256k(u-boot),256k(env),256k(header),16384k(bak),204800k(fs),286720k(rootfs_data)"
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#define MTDPARTITION_DEFAULT "nand0,4"
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#define ROOT_MTDBLOCK "/dev/mtdblock4"
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#define BOOT_FLASH_CMD "boot_flash=run setmtdparts flashargs addtty addmtd;fsload ${loadaddr} /boot/uImage;bootm ${loadaddr}\0"
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#define INIT_PROCESS_ENV "/etc/preinit"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"uboot_env_ver=" CONFIG_ENV_VERSION "\0" \
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"hostname=comcerto1000\0" \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"flashargs=setenv bootargs init=${init_process} root="ROOT_MTDBLOCK" rootfstype=${rootfstype} rw\0" \
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"rootfstype=jffs2\0" \
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"setmtdparts=setenv mtdparts " MTDPARTS_DEFAULT \
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"init_process=/etc/preinit\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off\0" \
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"addeth=setenv bootargs ${bootargs} " \
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"hwaddress=${netdev},${ethaddr}\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"flash_self=run flashargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;" \
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"bootm 80600000\0" \
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BOOT_FLASH_CMD \
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"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
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"rootpath=/devel/fs-zyxel-shg3305\0" \
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"kernelfile=uImage\0" \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"partition=" MTDPARTITION_DEFAULT "\0" \
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"mtddevnum=2\0" \
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"mtddevname=fs\0" \
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"fsfile=root.jffs2-128k\0" \
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"bootfile=u-boot.bin\0"\
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"updatenandfs=tftp 85000000 ${fsfile};nand erase 10C0000 ${filesize};nand write.jffs2 85000000 10c0000 ${filesize}\0" \
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"updatenandboot=tftp 85000000 ${bootfile};nand erase 0 40000;nand write.jffs2 85000000 0 40000\0" \
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"eepromfile=eeprom.bin\0" \
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"updateeprom=tftp 85000000 ${eepromfile};eeprom write 85000000 0 ${filesize}\0" \
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"bootcmd=run boot_flash\0"\
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"partition=nand0,4\0"\
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""
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/*-----------------------------------------------------------------------
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* JFFS2 Filesystem Configuration
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*/
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#define CONFIG_JFFS2_NAND 1
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#define CONFIG_JFFS2_DEV "nand0"
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_JFFS2_ULOAD
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//#define CONFIG_CMD_JFFS2_LS
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//#define CONFIG_CMD_JFFS2_FSINFO
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#define CONFIG_JFFS2_PART_OFFSET CFG_ROOTFS_PART_ADDR
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// Default using remaining flash space if you ignore 'CONFIG_JFFS_PART_SIZE'
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#define CONFIG_JFFS2_PART_SIZE CFG_ROOTFS_PART_SIZE
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/*-----------------------------------------------------------------------
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* Networking Configuration
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*/
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#define CONFIG_NET_MULTI 1
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#define CONFIG_NET_RETRY_COUNT 3
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#define CONFIG_COMCERTO_GEMAC 1
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#define CONFIG_GPHY_AR8035_DELAY_TUNING 1
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// GEMAC mode configured by bootstrap pins or SW
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#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
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//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
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#define GEMAC0_PHY_ADDR 4
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#define GEMAC0_CONFIG CONFIG_COMCERTO_USE_RGMII
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#define GEMAC0_MODE (GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
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#define GEMAC0_PHY_FLAGS (GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
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#define GEMAC0_PHYIDX 0
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#define GEMAC1_PHY_ADDR 5
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#define GEMAC1_CONFIG CONFIG_COMCERTO_USE_RGMII
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#define GEMAC1_MODE (GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
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#define GEMAC1_PHY_FLAGS (GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
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#define GEMAC1_PHYIDX 0
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#define CONFIG_MII
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#define CONFIG_CMD_MII
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#define CONFIG_PHY_GIGE
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C
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#define CONFIG_SYS_TCLK CFG_HZ_CLOCK
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#define CONFIG_SYS_I2C_SPEED 40000
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#define CONFIG_SYS_I2C_SLAVE 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* max 64 byte */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
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#if 0
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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//#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
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//#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
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//#define CONFIG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
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#undef CONFIG_FLASH_AM040_DRIVER /* disable AM040 flash driver */
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//#define CFG_FLASH_AMLV640U_DRIVER 1 /* enable AMLV640U flash driver */
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#undef CONFIG_FLASH_AMLV640U_DRIVER /* disable AMLV640U flash driver */
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#undef CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_MAX_FLASH_SECT 0x00020000 /* 128 KiB sectors */
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#undef CONFIG_FLASH_PROTECTION
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define PHYS_FLASH_1 EXP_CS0_BASEADDR /* Flash Bank #1 */
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#define PHYS_FLASH1_SECT_SIZE 0x00020000 /* 128 KiB sectors */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
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#define CONFIG_SYS_MONITOR_LEN (1 * PHYS_FLASH1_SECT_SIZE) /* Reserve 128 KiB for Monitor */
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//#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
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//#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#define CONFIG_SYS_JFFS2_MEM_NAND
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#endif
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/*-----------------------------------------------------------------------
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* Command line configuration.
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*/
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#define CONFIG_SYS_NO_FLASH
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#include <config_cmd_default.h>
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//=----------
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_NET
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//#define CONFIG_CMD_JFFS2
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//#define CONFIG_CMD_NFS
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//----------
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#undef CONFIG_CMD_BOOTD
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_EDITENV
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#undef CONFIG_CMD_SAVEENV
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/* Relocation options */
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//#define CONFIG_SKIP_RELOCATE_UBOOT
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif /* __CONFIG_H */
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