95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/*
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* Copyright Codito Technologies (www.codito.com)
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*
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* include/asm-arc/arcregs.h
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*
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* Copyright (C)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Authors: Sandeep Patil (sandeep.patil@codito.com)
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* Pradeep Sawlani (pradeep.sawlani@codito.com)
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* Auxiliary register definitions and macros to read and write to them.
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*/
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#ifndef _ASM_ARC_ARCDEFS_H
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#define _ASM_ARC_ARCDEFS_H
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/* These masks correspond to the status word(STATUS_32) bits */
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#define STATUS_H_SET 0x01 /* Mask for Halt bit */
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#define STATUS_E1_MASK 0x02 /* Mask for Interrupt 1 enable */
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#define STATUS_E2_MASK 0x04 /* Mask for Interrupt 2 enable */
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#define STATUS_DISABLE_INTERRUPTS 0xFFFFFFF9 /* Mask to disable Interrupts */
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/* Auxiliary register values */
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#define ARC_REG_STATUS32 0x0A /* status 32 register */
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#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
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#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
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#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
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#define ARC_REG_PC 0x06 /* program counter */
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/* MMU related Auxiliary registers */
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#define ARC_REG_DATA_UNCACHED 0x6A
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#define ARC_REG_TLBPD0 0x405
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#define ARC_REG_TLBPD1 0x406
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#define ARC_REG_TLBINDEX 0x407
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#define ARC_REG_TLBCOMMAND 0x408
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#define ARC_REG_PID 0x409
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/* Interrupt related Auxilliary registers */
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#define ARC_REG_INTR_VEC_BASE 0x25
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#define ARC_REG_INTR_ENABLE 0x40c
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/* Instruction cache related Auxiliary registers */
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#define ARC_REG_IC_BUILD_REG 0x77
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#define ARC_REG_IC_IVIC 0x10
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#define ARC_REG_IC_CTRL 0x11
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#define ARC_REG_IC_IVIL 0x19
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/* Data cache related Auxiliary registers */
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#define ARC_REG_DC_BUILD_REG 0x72
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#define ARC_REG_DC_IVDC 0x47
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#define ARC_REG_DC_CTRL 0x48
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#define ARC_REG_DC_IVDL 0x4A
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#define ARC_REG_DC_FLSH 0x4B
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#define ARC_REG_DC_FLDL 0x4C
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/* ARC_REG_DC_CTRL fields */
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#define ARC_INV_MODE_FLUSH 0x40
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#define ARC_DC_FLUSH_STATUS_BIT 0x100
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#define ARC_DC_DISABLE 0x01
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/* ARC_REG_IC_CTRL fields */
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#define ARC_IC_DISABLE 0x01
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/* Cache Line lengths fixed to 32 bytes */
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define ARC_ICACHE_LINE_LEN L1_CACHE_BYTES
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#define ARC_DCACHE_LINE_LEN L1_CACHE_BYTES
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/* Inline macros for reading, writing into auxiliary registers */
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#ifndef __ASSEMBLY__
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/* Read an auxiliary register */
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#define read_new_aux_reg(reg) \
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({ unsigned int __ret; \
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__asm__ __volatile__("lr %0, [%1]":"=r"(__ret):"i"(reg));\
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__ret; \
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})
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/* Write to an auxiliary register */
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#define write_new_aux_reg(reg, val) \
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({ \
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__asm__ __volatile__ ("sr %0, [%1]"::"r"(val),"i"(reg)); \
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})
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARC_ARCDEFS_H */
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