356 lines
14 KiB
C
356 lines
14 KiB
C
/*
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* arc_pgu.h - Register definitions for the ARC pixel graphics unit.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Copyright 2005 (C) ARC International (www.arc.com).
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*
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*/
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#ifndef _ASM_ARC_PGU_H
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#define _ASM_ARC_PGU_H
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/*--------------------------------------------------------------------------------------------*/
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/* Ioctl selectors FIXME - make sure these are unique within the fb subsystem */
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#define ARCPGUFB_GETYUV 0xffff0001
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#define ARCPGUFB_SETYUV 0xffff0002
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#define ARCPGUFB_FILLYUV 0xffff0003
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#define ARCPGUFB_SWITCH_YUV 0xffff0004
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#define ARCPGUFB_BKLGHT_OFF 0xffff0005
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#define ARCPGUFB_BKLGHT_ON 0xffff0006
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#define ARCPGUFB_START_DISPLAY 0xffff0007
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#define ARCPGUFB_STOP_DISPLAY 0xffff0008
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#define ARCPGUFB_GET_PGU_STATE 0xffff0009
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#define ARCPGUFB_SET_PGU_STATE 0xffff000a
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#define ARCPGUFB_GET_MAIN_MODE 0xffff000b
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#define ARCPGUFB_SET_MAIN_MODE 0xffff000c
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#define ARCPGUFB_SET_RGB_BUF 0xffff000d
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#define ARCPGUFB_GET_RGB_BUF 0xffff000e
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#define ARCPGUFB_GET_FB_MAIN 0xffff000f
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#define ARCPGUFB_CHECKPOINT 0xffff0010
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#define ARCPGUFB_RESTORE 0xffff0011
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#define ARCPGUFB_RESET 0xffff0012
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#define ARCPGUFB_SET_YUV_RES 0xffff0013
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#define ARCPGUFB_GET_FB_INFO 0xffff0014
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#define ARCPGUFB_SET_OL_MODE 0xffff0015
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#define ARCPGUFB_GET_OL_MODE 0xffff0016
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#define ARCPGUFB_GET_OL_COLKEY 0xffff0017
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#define ARCPGUFB_SET_OL_COLKEY 0xffff0018
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#define ARCPGUFB_GET_OL_START 0xffff0019
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#define ARCPGUFB_SET_OL_START 0xffff001a
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#define ARCPGUFB_GET_OL_END 0xffff001b
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#define ARCPGUFB_SET_OL_END 0xffff001c
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#define ARCPGUFB_SET_OL_OFFSET 0xffff001d
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#define ARCPGUFB_GET_YUV_BASE 0xffff002c /* return address of yuv buffer n */
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#ifdef CONFIG_ENABLE_CENTERING
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#define ARCPGUFB_GET_ORIGIN 0xffff001e
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#define ARCPGUFB_SET_ORIGIN 0xffff001f
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#endif
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#define ARCPGUFB_ALLOC 0xffff0020
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#define ARCPGUFB_FREE 0xffff0021
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#define ARCPGUFB_SEND 0xffff0022
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#define ARCPGUFB_FRAMERATE_SET 0xffff0023
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#define ARCPGUFB_QUEUE_LEN_GET 0xffff0024
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#define ARCPGUFB_FLUSH 0xffff0025
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#define ARCPGUFB_FRAME_DROP 0xffff0026
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#define ARCPGUFB_PAUSE 0xffff0027
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#define ARCPGUFB_RESUME 0xffff0028
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#define ARCPGUFB_RESET_SYNC 0xffff0029
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#define ARCPGUFB_NUM_FREE_BUFS 0xffff002a
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#define ARCPGUFB_PAUSE_MS 0xffff002b
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#define ARCPGUFB_GET_STATCTRL 0xffff00fe
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#define ARCPGUFB_SET_STATCTRL 0xffff00ff
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/*--------------------------------------------------------------------------------------------*/
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/* YUV buffer layout - all sizes and offsets in bytes. Note that base addresses tend to be
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passed around as unsigned longs, in which case you'll need to typecast before applying
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any offsets. */
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struct yuv_info {
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unsigned int displayed_buffer;
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unsigned long phys_base;
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unsigned long virt_base;
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unsigned long yuv_size;
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unsigned long alignment;
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unsigned long num_buffers;
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unsigned long start_offset;
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unsigned long width;
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unsigned long height;
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unsigned long u_offset;
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unsigned long v_offset;
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unsigned long y_stride;
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unsigned long u_stride;
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unsigned long v_stride;
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#ifdef CONFIG_ARC_PGU_CROPPING
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unsigned long cropped_width;
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unsigned long cropped_height;
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unsigned long x_offset;
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unsigned long y_offset;
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#endif
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};
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/*--------------------------------------------------------------------------------------------*/
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/* Register definitions */
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/* Base+0x00 PGU_MODULE_ID Register containing read only module ID and
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* Revision numbers */
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#define PGU_MODULE_ID_OFFSET 0x0
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#define PGU_DISPLAY_TYPE_MASK 0x1000000
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#define PGU_VERSION_MASK 0xff0000
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#define PGU_VERSION_SHIFT 16
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/* Base+0x08 CLK_CFG_REG Clock Configuration register. It is used to
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* Define the clock divider value, and the
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* pulse width (high cycle) in clock cycles:
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* [ 7: 0] CLK_DIV : clock divider value - 1
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* [23:16] CLK_HIGH : High pulse width - 1 */
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#define CLK_CFG_REG_OFFSET 0x8
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#define CLK_CFG_REG_CLK_DIV_MASK 0xff
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#define CLK_CFG_REG_CLK_HIGH_MASK 0xff0000
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#define GET_CLK_CFG_REG_CLK_HIGH_VAL(x) (x & CLK_CFG_REG_CLK_HIGH_MASK) >> 16
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#define SET_CLK_CFG_REG_CLK_HIGH_VAL(x, y) (x & !CLK_CFG_REG_CLK_HIGH_MASK) | ((y << 16) & CLK_CFG_REG_CLK_HIGH_MASK)
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/* Base+0x10 DISP_DIM_REG Display Dimensions register. This specify
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* the dimensions of the actual display.
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* [10: 0] PGU_X_RES : X dimension - 1
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* [26:16] PGU_Y_RES : Y dimension - 1 */
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#define DISP_DIM_REG_OFFSET 0x10
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#define DISP_DIM_REG_PGU_X_RES_MASK 0x3ff
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#define DISP_DIM_REG_PGU_Y_RES_MASK 0x3ff0000
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#define DISP_DIM_Y_SHIFT 16
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#define ENCODE_PGU_DIMS(x,y) ((x & DISP_DIM_REG_PGU_X_RES_MASK) | ((y & DISP_DIM_REG_PGU_X_RES_MASK) * 0x10000))
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/* Base+0x18 HSYNC_CFG_REG Hsync Configuration register. This is used
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* to specify various hsync related timings in
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* clock cycles:
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* [11: 0] HSYNC_CYC : Hsync period - 1
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* [23:16] H_BCK_PORTH : Back porth width - 1
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* [31:23] HSYNC_WIDTH : Hsync low width - 1 */
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#define PGU_SYNC_REGS_CYC_MASK 0xfff
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#define PGU_SYNC_REGS_PORCH_MASK 0xff0000
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#define PGU_SYNC_REGS_WIDTH_MASK 0xff000000
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#define PGU_SYNC_REGS_PORCH_OFFSET 16
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#define PGU_SYNC_REGS_WIDTH_OFFSET 24
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#define HSYNC_CFG_REG_OFFSET 0x18
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/* Base+0x20 VSYNC_CFG_REG Vsync Configuration register. This is used
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* to specify various Vsync related timings in
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* Hsync cycles:
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* [11: 0] VSYNC_CYC : Vsync period - 1
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* [23:16] V_BCK_PORTH : Back porth width - 1
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* [31:23] VSYNC_WIDTH : Hsync low width */
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#define VSYNC_CFG_REG_OFFSET 0x20
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/* Base+0x28 FRMSTART_REG Frame Start Address. This 32 bit address
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* specifies the start of the display frame
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* in memory. Must be at least 2 byte aligned
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* for 16 bit per pixel format. */
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#define FRMSTART_REG_OFFSET 0x28
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/* Base+0x30 STRIDE_REG Line Stride Address. This 32 bit address
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* specifies the different in address between
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* the first pixels of adjecent display lines
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* in memory. Must be at least 2 byte aligned
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* for 16 bit per pixel format. */
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#define STRIDE_REG_OFFSET 0x30
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/* Base+0x38 FRM_DIM_REG Frame Dimension register. This register
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* defines the frame size of the display in
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* memory and can be smaller than the display.
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* [10:0] FRM_WTH : frame line width in
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* pixels. Must be <=
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* PGU_X_RES without x2 mode
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* or <= PGU_X_RES/2 in x2
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* mode.
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* [26:16] FRM_LNS : frame number of lines
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* Must be <= PGU_X_RES
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* without x2 mode or <=
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* PGU_X_RES/2 in x2 mode. */
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#define FRM_DIM_REG_OFFSET 0x38
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#define FRM_DIM_REG_FRM_WTH_MASK 0x7ff
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#define FRM_DIM_REG_FRM_LNS_MASK 0x7ff
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/*
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* Base+0x40 STATCTRL_REG Status and Control register. This register
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* is used to control the display module and
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* monitor its status: */
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#define STATCTRL_REG_OFFSET 0x40
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/* [0] DISP_EN : Display enable bit. When
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* set to high, starts the
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* display. It then clears
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* after a few cycles, if
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* the CONT bit is not set,
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* hence allowing the display
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* to do the frame once. */
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#define STATCTRL_REG_DISP_EN_MASK 1
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/* [1] INTR_EN : Interrupt Enable. Active
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* high. */
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#define STATCTRL_INTR_EN_MASK 2
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/* [2] INTR_CLR : Interrupt Clear. Set to
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* high to clear the interrupt
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* flag/request. Always reads
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* as zeros */
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#define STATCTRL_INTR_CLR_MASK 4
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/* [3] CONT : Continuous mode. When set,
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* will not allow the DISP_EN
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* bit to be cleared by itself
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* and as long as DISP_EN is
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* not cleared manually, the
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* Dispaly will drive the PGU
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* continuously, frame after
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* frame. */
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#define STATCTRL_CONT_B_MASK 8
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/* [5:4] PIX_FMT Pixel Format. Select the
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* pixel format:
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* "00" - RGB555
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* "01" - YUV420 (aka YV12)
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* "10" - reserved
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* "11" - reserved */
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#define STATCTRL_PIX_FMT_MASK 0x30
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#define STATCTRL_PIX_FMT_OFFSET 4
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#define STATCTRL_PIX_FMT_RGB555 0
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#define STATCTRL_PIX_FMT_YUV420 0x10
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/* [6] BACKLIGHT Active high backlight
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* enable. When set to high,
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* sets the back light control
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* signal to high to turn on
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* the backlight of the PGU. */
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#define STATCTRL_BACKLIGHT_MASK 0x40
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/* [7] X2 Zoom 2 mode. when set,
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* every pixel in the frame is
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* display twice in a line &
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* the line is displayed twice
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* therefore enlarging the
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* picture. */
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#define STATCTRL_X2_MASK 0x80
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/* [8] REV_LN_SCAN Reverse line scan. When set
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* the display displays the
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* last line first, back
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* towards the first */
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#define STATCTRL_REV_LN_SCAN_MASK 0x100
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/* [9] HPOL HSync signal polarity */
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#define STATCTRL_HPOL_MASK 0x200
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/* [10] VPOL VSync signal polarity */
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#define STATCTRL_VPOL_MASK 0x400
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/* [11] DPOL Data enable signal polarity */
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#define STATCTRL_DPOL_MASK 0x800
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/* [12] OL_EN Overlay enable */
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#define STATCTRL_OL_EN_MASK 0x1000
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/* [13-15] OL_FMT Overlay format:
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* "00" - RGBA4444
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* "01" - RGBA5551
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* "10" - RGB555 with colour keying */
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#define STATCTRL_OL_FMT_MASK 0x6000
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#define STATCTRL_OL_FMT_OFFSET 13
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#define STATCTRL_OL_FMT_RGBA4444 0
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#define STATCTRL_OL_FMT_RGBA5551 0x2000
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#define STATCTRL_OL_FMT_RGB555 0x4000
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/* [16] DISP_BUSY Display Busy status. Active
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* High. When set indicates
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* that the display is
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* currently scanning out
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* pixel data, or generating
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* syncs for the current
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* display */
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#define STATCTRL_DISP_BUSY_MASK 0x10000
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/* [17] BU_BUSY Burst Unit busy. Active
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* high. When set indicates
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* that the burst unit is
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* busy fetching pixel data. */
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#define STATCTRL_BU_BUSY_MASK 0x20000
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/* [18] INTR_FLG Interrupt flag. Refelects
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* the interrupt signal.
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* Active low level interrupt. */
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#define STATCTRL_INTR_FLAG 0x40000
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/* [19-20] IL_MD Interface mode select
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* "00" - Non-interlaced
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* "01" - Frame mode interlace
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* "10" - Even field interlace
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* "11" - Odd field interlace */
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#define STATCTRL_IL_MODE_MASK 0x180000
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#define STATCTRL_IL_NONE 0
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#define STATCTRL_IL_FRAME 0x80000
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#define STATCTRL_IL_EVEN 0x100000
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#define STATCTRL_IL_ODD 0x180000
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/*--------------------------------------------------------------------------------------------*/
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typedef volatile struct {
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volatile unsigned long pgu_id; /* Identity register */
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volatile unsigned long padding1;
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volatile unsigned long clk_cfg; /* Clock control */
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volatile unsigned long padding2;
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volatile unsigned long disp_dim; /* Display dimension */
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volatile unsigned long padding3;
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volatile unsigned long hsync_cfg; /* HSYNC */
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volatile unsigned long padding4;
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volatile unsigned long vsync_cfg; /* VSYNC */
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volatile unsigned long padding5;
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volatile unsigned long frm_start; /* Frame start */
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volatile unsigned long padding6;
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volatile unsigned long stride; /* Frame stride */
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volatile unsigned long padding7;
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volatile unsigned long frm_dim; /* Frame dimension */
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volatile unsigned long padding8;
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volatile unsigned long statctrl; /* Status and control */
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volatile unsigned long padding9;
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volatile unsigned long cru_frm_st; /* Chroma U frame start */
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volatile unsigned long padding10;
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volatile unsigned long cru_stride; /* Chroma U stride */
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volatile unsigned long padding11;
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volatile unsigned long crv_frm_st; /* Chroma V frame start */
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volatile unsigned long padding12;
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volatile unsigned long crv_stride; /* Chroma V stride */
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#ifdef CONFIG_ENABLE_ARCPGU_OVERLAY
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volatile unsigned long padding13;
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volatile unsigned long ol_frm_st; /* Overlay frame start */
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volatile unsigned long padding14;
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volatile unsigned long ol_stride; /* Overlay stride */
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volatile unsigned long padding15;
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volatile unsigned long ol_scn_line; /* Overlay start and end line numbers */
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volatile unsigned long padding16;
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volatile unsigned long ol_col_key; /* Overlay transparency colour key - RGB 555 */
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#endif
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#ifdef CONFIG_ENABLE_CENTERING
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volatile unsigned long padding17;
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volatile unsigned long centreoffsets; /* X, Y offsets for centering */
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#endif
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} arc_pgu;
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/*--------------------------------------------------------------------------------------------*/
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#endif /* _ASM_ARC_PGU_H */
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