591 lines
16 KiB
C
591 lines
16 KiB
C
#include <common.h>
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#include <command.h>
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#include <asm/arch/rt_mmap.h>
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#define outw(address, value) *((volatile uint32_t *)(address)) = cpu_to_le32(value)
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#define inw(address) le32_to_cpu(*(volatile u32 *)(address))
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
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#define PHY_CONTROL_0 0xC0
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#define PHY_CONTROL_1 0xC4
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#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
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#define MDIO_PHY_CONTROL_1 (RALINK_ETH_SW_BASE + PHY_CONTROL_1)
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#define GPIO_MDIO_BIT (1<<7)
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#define GPIO_PURPOSE_SELECT 0x60
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#define GPIO_PRUPOSE (RALINK_SYSCTL_BASE + GPIO_PURPOSE_SELECT)
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#elif defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \
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defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) || \
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defined (RT6352_FPGA_BOARD) || defined (RT6352_ASIC_BOARD) || \
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defined (RT71100_FPGA_BOARD) || defined (RT71100_ASIC_BOARD)
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#define PHY_CONTROL_0 0x7004
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#define PHY_CONTROL_1 0x7000
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#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
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#define MDIO_PHY_CONTROL_1 (RALINK_ETH_SW_BASE + PHY_CONTROL_1)
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#define GPIO_MDIO_BIT (1<<7)
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#define GPIO_PURPOSE_SELECT 0x60
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#define GPIO_PRUPOSE (RALINK_SYSCTL_BASE + GPIO_PURPOSE_SELECT)
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#else
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#define PHY_CONTROL_0 0x00
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#define PHY_CONTROL_1 0x04
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#define MDIO_PHY_CONTROL_0 (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_0)
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#define MDIO_PHY_CONTROL_1 (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_1)
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#define enable_mdio(x)
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#endif
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \
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defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \
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defined (RT6352_FPGA_BOARD) || defined (RT6352_ASIC_BOARD) || \
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defined (RT71100_FPGA_BOARD) || defined (RT71100_ASIC_BOARD)
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void enable_mdio(int enable)
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{
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#if !defined (P5_MAC_TO_PHY_MODE)
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u32 data = inw(GPIO_PRUPOSE);
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if(enable)
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data &= ~GPIO_MDIO_BIT;
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else
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data |= GPIO_MDIO_BIT;
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outw(GPIO_PRUPOSE, data);
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#endif
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}
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#endif
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#if defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD)
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#define enable_mdio(x)
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#endif
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#if defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \
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defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) || \
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defined (RT6352_FPGA_BOARD) || defined (RT6352_ASIC_BOARD) || \
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defined (RT71100_FPGA_BOARD) || defined (RT71100_ASIC_BOARD)
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int mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
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{
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u32 volatile status = 0;
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u32 volatile data = 0;
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u32 rc = 0;
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unsigned long volatile t_start = get_timer(0);
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/* We enable mdio gpio purpose register, and disable it when exit. */
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enable_mdio(1);
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//printf("\n MDIO Read operation!!\n");
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// make sure previous read operation is complete
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while(1)
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{
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// 0 : Read/write operation complet
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if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
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{
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break;
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}else if(get_timer(t_start) > (5 * CONFIG_SYS_HZ)){
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enable_mdio(0);
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printf("\n MDIO Read operation is ongoing !!\n");
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return rc;
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}
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}
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data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
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outw(MDIO_PHY_CONTROL_0, data);
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data |= (1<<31);
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outw(MDIO_PHY_CONTROL_0, data);
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//printf("\n Set Command [0x%08X] to PHY 0x%8x!!\n", data, MDIO_PHY_CONTROL_0);
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// make sure read operation is complete
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t_start = get_timer(0);
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while(1)
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{
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if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
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{
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udelay(100000);
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status = inw(MDIO_PHY_CONTROL_0);
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*read_data = (u32)(status & 0x0000FFFF);
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//printf("\n MDIO_PHY_CONTROL_0: 0x%8x!!\n", status);
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enable_mdio(0);
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return 1;
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}
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else if(get_timer(t_start) > (5 * CONFIG_SYS_HZ))
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{
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enable_mdio(0);
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printf("\n MDIO Read operation is ongoing and Time Out!!\n");
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return 0;
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}
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}
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}
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int mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
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{
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unsigned long volatile t_start=get_timer(0);
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u32 volatile data;
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enable_mdio(1);
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// make sure previous write operation is complete
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while(1)
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{
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if (!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
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{
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break;
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}
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else if(get_timer(t_start) > (5 * CONFIG_SYS_HZ))
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{
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enable_mdio(0);
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printf("\n MDIO Write operation is ongoing !!\n");
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return 0;
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}
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}
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data = (0x01 << 16) | (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
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outw(MDIO_PHY_CONTROL_0, data);
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data |= (1<<31);
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outw(MDIO_PHY_CONTROL_0, data); //start operation
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//printf("\n Set Command [0x%08X] to PHY 0x%8x!!\n", data, MDIO_PHY_CONTROL_0);
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t_start = get_timer(0);
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// make sure write operation is complete
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while(1)
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{
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if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31))) // 0 : Read/write operation complete
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{
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enable_mdio(0);
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return 1;
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}
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else if(get_timer(t_start) > (5 * CONFIG_SYS_HZ))
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{
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enable_mdio(0);
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printf("\n MDIO Write operation is ongoing and Time Out!!\n");
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return 0;
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}
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}
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}
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#else
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int mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
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{
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u32 volatile status = 0;
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u32 volatile data = 0;
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u32 rc = 0;
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unsigned long volatile t_start = get_timer(0);
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/* We enable mdio gpio purpose register, and disable it when exit. */
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enable_mdio(1);
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// make sure previous read operation is complete
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while(1)
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{
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
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// rd_rdy: read operation is complete
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if(!( inw(MDIO_PHY_CONTROL_1) & (0x1 << 1)))
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#else
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// 0 : Read/write operation complet
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if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
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#endif
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{
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break;
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}else if(get_timer(t_start) > (5 * CONFIG_SYS_HZ)){
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enable_mdio(0);
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printf("\n MDIO Read operation is ongoing !!\n");
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return rc;
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}
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}
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
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outw(MDIO_PHY_CONTROL_0 , (1<<14) | (phy_register << 8) | (phy_addr));
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#else
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data = (phy_addr << 24) | (phy_register << 16);
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outw(MDIO_PHY_CONTROL_0, data);
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data |= (1<<31);
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outw(MDIO_PHY_CONTROL_0, data);
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#endif
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//printf("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
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// make sure read operation is complete
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t_start = get_timer(0);
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while(1)
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{
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
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if( inw(MDIO_PHY_CONTROL_1) & (0x1 << 1))
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{
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status = inw(MDIO_PHY_CONTROL_1);
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*read_data = (u32)(status >>16);
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enable_mdio(0);
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return 1;
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}
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#else
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if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
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{
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status = inw(MDIO_PHY_CONTROL_0);
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*read_data = (u32)(status & 0x0000FFFF);
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enable_mdio(0);
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return 1;
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}
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#endif
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else if(get_timer(t_start) > (5 * CONFIG_SYS_HZ))
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{
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enable_mdio(0);
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printf("\n MDIO Read operation is ongoing and Time Out!!\n");
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return 0;
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}
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}
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}
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int mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
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{
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unsigned long volatile t_start=get_timer(0);
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u32 volatile data;
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enable_mdio(1);
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// make sure previous write operation is complete
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while(1)
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{
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \
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defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \
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defined (RT6352_FPGA_BOARD) || defined (RT6352_ASIC_BOARD) || \
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defined (RT71100_FPGA_BOARD) || defined (RT71100_ASIC_BOARD)
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if(!( inw(MDIO_PHY_CONTROL_1) & (0x1 << 0)))
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#else
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if (!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
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#endif
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{
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break;
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}
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else if(get_timer(t_start) > (5 * CONFIG_SYS_HZ))
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{
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enable_mdio(0);
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printf("\n MDIO Write operation is ongoing !!\n");
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return 0;
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}
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}
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
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data = ((write_data & 0xFFFF)<<16);
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data |= (phy_register << 8) | (phy_addr);
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data |= (1<<13);
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outw(MDIO_PHY_CONTROL_0, data);
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#else
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data = (1<<30) | (phy_addr << 24) | (phy_register << 16) | write_data;
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outw(MDIO_PHY_CONTROL_0, data);
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data |= (1<<31);
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outw(MDIO_PHY_CONTROL_0, data); //start operation
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#endif
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//printf("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
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t_start = get_timer(0);
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// make sure write operation is complete
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while(1)
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{
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
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if( inw(MDIO_PHY_CONTROL_1) & (0x1 << 0)) //wt_done ?= 1
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#else
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if(!( inw(MDIO_PHY_CONTROL_0) & (0x1 << 31))) // 0 : Read/write operation complete
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#endif
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{
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enable_mdio(0);
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return 1;
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}
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else if(get_timer(t_start) > (5 * CONFIG_SYS_HZ))
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{
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enable_mdio(0);
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printf("\n MDIO Write operation is ongoing and Time Out!!\n");
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return 0;
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}
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}
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}
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#endif
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#ifdef RALINK_MDIO_ACCESS_FUN
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#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
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defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
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defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
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void dump_phy_reg(int port_no, int from, int to, int is_local)
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{
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u32 i=0;
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u32 temp=0;
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if(is_local==0) {
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printf("Global Register\n");
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printf("===============");
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mii_mgr_write(0, 31, 0); //select global register
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for(i=from;i<=to;i++) {
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if(i%8==0) {
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printf("\n");
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}
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mii_mgr_read(port_no,i, &temp);
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printf("%02d: %04X ",i, temp);
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}
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} else {
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mii_mgr_write(0, 31, 0x8000); //select local register
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printf("\n\nLocal Register Port %d\n",port_no);
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printf("===============");
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for(i=from;i<=to;i++) {
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if(i%8==0) {
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printf("\n");
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}
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mii_mgr_read(port_no,i, &temp);
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printf("%02d: %04X ",i, temp);
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}
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}
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printf("\n");
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}
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#else
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void dump_phy_reg(int port_no, int from, int to, int is_local, int page_no)
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{
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u32 i=0;
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u32 temp=0;
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u32 r31=0;
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if(is_local==0) {
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printf("\n\nGlobal Register Page %d\n",page_no);
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printf("===============");
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r31 = 0 << 15; //global
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r31 = page_no&0x7 << 12; //page no
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mii_mgr_write(0, 31, r31); //select global page x
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for(i=16;i<32;i++) {
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if(i%8==0) {
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printf("\n");
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}
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mii_mgr_read(port_no,i, &temp);
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printf("%02d: %04X ",i, temp);
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}
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}else {
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printf("\n\nLocal Register Port %d Page %d\n",port_no, page_no);
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printf("===============");
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r31 = 1 << 15; //local
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r31 = page_no&0x7 << 12; //page no
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mii_mgr_write(0, 31, r31); //select local page x
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for(i=16;i<32;i++) {
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if(i%8==0) {
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printf("\n");
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}
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mii_mgr_read(port_no,i, &temp);
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printf("%02d: %04X ",i, temp);
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}
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}
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printf("\n");
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}
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#endif
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int rt2880_mdio_access(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u32 addr;
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u32 phy_addr;
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u32 value = 0,bit_offset,temp;
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u32 i=0;
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if(!memcmp(argv[0],"mdio.anoff",sizeof("mdio.anoff")))
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{
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#if defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \
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defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) || \
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defined (RT6352_FPGA_BOARD) || defined (RT6352_ASIC_BOARD) || \
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defined (RT71100_FPGA_BOARD) || defined (RT71100_ASIC_BOARD)
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value = inw(MDIO_PHY_CONTROL_1);
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value &= ~(1 << 31);
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outw(MDIO_PHY_CONTROL_1,value);
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puts("\n GMAC1 Force link status enable !! \n");
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#else
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value = inw(MDIO_PHY_CONTROL_1);
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value |= (1<<15);
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outw(MDIO_PHY_CONTROL_1,value);
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puts("\n GMAC1 Force link status enable !! \n");
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#endif
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}
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else if(!memcmp(argv[0],"mdio.anon",sizeof("mdio.anon")))
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{
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#if defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \
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defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) || \
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defined (RT6352_FPGA_BOARD) || defined (RT6352_ASIC_BOARD) || \
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defined (RT71100_FPGA_BOARD) || defined (RT71100_ASIC_BOARD)
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value = inw(MDIO_PHY_CONTROL_1);
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value |= (1<<31);
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outw(MDIO_PHY_CONTROL_1,value);
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puts("\n GMAC1 Force link status disable !! \n");
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#else
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value = inw(MDIO_PHY_CONTROL_1);
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value &= ~(1 << 15);
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outw(MDIO_PHY_CONTROL_1,value);
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puts("\n GMAC1 Force link status disable !! \n");
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#endif
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}
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else if(!memcmp(argv[0],"mdio.r",sizeof("mdio.r")))
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{
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if (argc != 3) {
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 1;
|
|
}
|
|
phy_addr = simple_strtoul(argv[1], NULL, 10);
|
|
addr = simple_strtoul(argv[2], NULL, 10);
|
|
phy_addr &=0x1f;
|
|
|
|
if(mii_mgr_read(phy_addr, addr, &value))
|
|
printf("\n mdio.r addr[0x%08X]=0x%04X\n",addr,value);
|
|
else {
|
|
printf("\n Read addr[0x%08X] is Fail!!\n",addr);
|
|
}
|
|
}
|
|
else if(!memcmp(argv[0],"mdio.w",sizeof("mdio.w")))
|
|
{
|
|
if (argc != 4) {
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 1;
|
|
}
|
|
phy_addr = simple_strtoul(argv[1], NULL, 10);
|
|
addr = simple_strtoul(argv[2], NULL, 10);
|
|
value = simple_strtoul(argv[3], NULL, 16);
|
|
phy_addr &=0x1f;
|
|
|
|
if(mii_mgr_write(phy_addr, addr,value)) {
|
|
printf("\n mdio.w addr[0x%08X] value[0x%08X]\n",addr,value);
|
|
}
|
|
else {
|
|
printf("\n Write[0x%08X] is Fail!!\n",addr);
|
|
}
|
|
}
|
|
else if(!memcmp(argv[0],"mdio.wb",sizeof("mdio.wb")))
|
|
{
|
|
if (argc != 4) {
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 1;
|
|
}
|
|
addr = simple_strtoul(argv[1], NULL, 10);
|
|
bit_offset = simple_strtoul(argv[2], NULL, 10);
|
|
value = simple_strtoul(argv[3], NULL, 10);
|
|
|
|
if(mii_mgr_read(31, addr,&temp)) {
|
|
|
|
}
|
|
else {
|
|
printf("\n Rasd PHY fail while mdio.wb was called\n");
|
|
return 1;
|
|
}
|
|
|
|
if(value) {
|
|
printf("\n Set bit[%d] to '1' \n",bit_offset);
|
|
temp |= (1<<bit_offset);
|
|
}
|
|
else {
|
|
printf("\n Set bit[%d] to '0' \n",bit_offset);
|
|
temp &= ~(1<<bit_offset);
|
|
}
|
|
|
|
if(mii_mgr_write(31, addr,temp)) {
|
|
printf("\n mdio.wb addr[0x%08X] value[0x%08X]\n",addr,temp);
|
|
}
|
|
else {
|
|
printf("\n Write[0x%08X] is Fail!!\n",addr);
|
|
}
|
|
}
|
|
else if(!memcmp(argv[0],"mdio.d",sizeof("mdio.d")))
|
|
{
|
|
#if defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) || \
|
|
defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \
|
|
defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD)
|
|
if (argc == 2) {
|
|
addr = simple_strtoul(argv[1], NULL, 10);
|
|
dump_phy_reg(0, 0, 31, 0); //dump global register
|
|
dump_phy_reg(addr, 0, 31, 1); //dump local register
|
|
}else {
|
|
/* Global Register 0~31
|
|
* Local Register 0~31
|
|
*/
|
|
dump_phy_reg(0, 0, 31, 0); //dump global register
|
|
for(i=0;i<5;i++) {
|
|
dump_phy_reg(i, 0, 31, 1); //dump local register
|
|
}
|
|
}
|
|
#else //RT6855A, RT6855, RT6352, RT71100
|
|
/* SPEC defined Register 0~15
|
|
* Global Register 16~31 for each page
|
|
* Local Register 16~31 for each page
|
|
*/
|
|
printf("SPEC defined Register\n");
|
|
printf("===============");
|
|
for(i=0;i<=16;i++) {
|
|
if(i%8==0) {
|
|
printf("\n");
|
|
}
|
|
mii_mgr_read(0,i, &temp);
|
|
printf("%02d: %04X ",i, temp);
|
|
}
|
|
|
|
if (argc == 2) {
|
|
addr = simple_strtoul(argv[1], NULL, 10);
|
|
dump_phy_reg(addr, 16, 31, 0, i);
|
|
dump_phy_reg(addr, 16, 31, 1, 0); //dump local page 0
|
|
dump_phy_reg(addr, 16, 31, 1, 1); //dump local page 1
|
|
dump_phy_reg(addr, 16, 31, 1, 2); //dump local page 2
|
|
dump_phy_reg(addr, 16, 31, 1, 3); //dump local page 3
|
|
}else {
|
|
|
|
for(i=0;i<4;i++) { //global register page 0~4
|
|
dump_phy_reg(0, 16, 31, 0, i);
|
|
}
|
|
|
|
for(i=0;i<5;i++) { //local register port 0-port4
|
|
dump_phy_reg(i, 16, 31, 1, 0); //dump local page 0
|
|
dump_phy_reg(i, 16, 31, 1, 1); //dump local page 1
|
|
dump_phy_reg(i, 16, 31, 1, 2); //dump local page 2
|
|
dump_phy_reg(i, 16, 31, 1, 3); //dump local page 3
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
mdio, 4, 1, rt2880_mdio_access,
|
|
"mdio - Ralink PHY register R/W command !!\n",
|
|
"mdio.r [phy_addr(dec)] [reg_addr(dec)] \n"
|
|
"mdio.w [phy_addr(dec)] [reg_addr(dec)] [data(HEX)] \n"
|
|
"mdio.anoff GMAC1 Force link status enable !! \n"
|
|
"mdio.anon GMAC1 Force link status disable !! \n"
|
|
"mdio.wb [phy register(dec)] [bit offset(Dec)] [Value(0/1)] \n"
|
|
"mdio.d - dump all Phy registers \n"
|
|
"mdio.d [phy register(dec)] - dump Phy registers \n"
|
|
);
|
|
#endif // RALINK_MDIO_ACCESS_FUN //
|
|
|