298 lines
6.5 KiB
C
298 lines
6.5 KiB
C
#include <common.h>
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#include <command.h>
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#include <asm/arch/rt_mmap.h>
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#define SOFTRES_REG (RALINK_SYSCTL_BASE + 0x0034)
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#define GORESET (0x01)
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unsigned long mips_cpu_feq;
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unsigned long mips_bus_feq;
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void _machine_restart(void)
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{
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#if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD)
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ra_outl(RALINK_TIMER_BASE + 0x2c, 0x1); //timer3 load value
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ra_or(RALINK_TIMER_BASE, (1 << 5) | (1 << 25)); //timer3 enabled as watchdog
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#else
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*(volatile unsigned int*)(SOFTRES_REG) = GORESET;
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#endif
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}
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void rt2880_freq_calculate(void)
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{
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u32 reg;
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#ifdef ASIC_BOARD
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u8 clk_sel __maybe_unused, clk_sel2 __maybe_unused;
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#endif
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reg = RALINK_REG(RT2880_SYSCFG_REG);
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/*
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* CPU_CLK_SEL (bit 21:20)
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*/
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#ifdef RT2880_FPGA_BOARD
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mips_cpu_feq = 25 * 1000 *1000;
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mips_bus_feq = mips_cpu_feq/2;
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#elif defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD) || defined (RT3352_FPGA_BOARD) || defined (RT5350_FPGA_BOARD)
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mips_cpu_feq = 40 * 1000 *1000;
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mips_bus_feq = mips_cpu_feq/3;
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#elif defined (RT6855A_FPGA_BOARD)
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mips_cpu_feq = 50 * 1000 *1000;
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mips_bus_feq = mips_cpu_feq/2;
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#elif defined (RT3883_FPGA_BOARD)
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mips_cpu_feq = 40 * 1000 *1000;
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mips_bus_feq = mips_cpu_feq;
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#elif defined (RT6855_FPGA_BOARD) || defined (RT6352_FPGA_BOARD) || defined (RT71100_FPGA_BOARD)
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/* FIXME */
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mips_cpu_feq = 50 * 1000 *1000;
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mips_bus_feq = mips_cpu_feq/4;
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#elif defined (RT2883_ASIC_BOARD)
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clk_sel = (reg>>20) & 0x03;
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switch(clk_sel) {
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case 0:
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mips_cpu_feq = (380*1000*1000);
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break;
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case 1:
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mips_cpu_feq = (400*1000*1000);
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break;
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case 2:
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mips_cpu_feq = (420*1000*1000);
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break;
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case 3:
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mips_cpu_feq = (430*1000*1000);
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break;
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}
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mips_bus_feq = mips_cpu_feq/2;
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#elif defined(RT3052_ASIC_BOARD)
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#if defined(RT3350_ASIC_BOARD)
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//MA10 is floating
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mips_cpu_feq = (320*1000*1000);
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#else
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clk_sel = (reg>>18) & 0x01;
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switch(clk_sel) {
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case 0:
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mips_cpu_feq = (320*1000*1000);
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break;
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case 1:
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mips_cpu_feq = (384*1000*1000);
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break;
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}
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#endif
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mips_bus_feq = mips_cpu_feq / 3;
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#elif defined(RT3352_ASIC_BOARD)
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clk_sel = (reg>>8) & 0x01;
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switch(clk_sel) {
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case 0:
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mips_cpu_feq = (384*1000*1000);
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break;
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case 1:
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mips_cpu_feq = (400*1000*1000);
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break;
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}
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mips_bus_feq = (133*1000*1000);
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#elif defined(RT5350_ASIC_BOARD)
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clk_sel2 = (reg>>10) & 0x01;
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clk_sel = ((reg>>8) & 0x01) + (clk_sel2 * 2);
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switch(clk_sel) {
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case 0:
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mips_cpu_feq = (360*1000*1000);
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mips_bus_feq = (120*1000*1000);
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break;
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case 1:
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//reserved
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break;
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case 2:
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mips_cpu_feq = (320*1000*1000);
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mips_bus_feq = (80*1000*1000);
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break;
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case 3:
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mips_cpu_feq = (300*1000*1000);
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mips_bus_feq = (100*1000*1000);
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break;
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}
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#elif defined(RT6855_ASIC_BOARD)
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mips_cpu_feq = (400*1000*1000);
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mips_bus_feq = (133*1000*1000);
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#elif defined (RT6855A_ASIC_BOARD)
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/* FPGA is 25/32Mhz
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* ASIC RT6856/RT6856A: DDR(0): 233.33, DDR(1): 175, SDR: 140
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* RT6855/RT6855A: DDR(0): 166.67, DDR(1): 125, SDR: 140 */
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reg = RALINK_REG(RT2880_SYSCFG_REG);
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if ((reg & (1 << 25)) == 0) { /* SDR */
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if ((reg & (1 << 9)) != 0)
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mips_cpu_feq = (560*1000*1000);
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else {
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if ((reg & (1 << 26)) != 0)
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mips_cpu_feq = (560*1000*1000);
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else
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mips_cpu_feq = (420*1000*1000);
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}
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mips_bus_feq = (140*1000*1000);
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} else { /* DDR */
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if ((reg & (1 << 9)) != 0) {
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mips_cpu_feq = (700*1000*1000);
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if ((reg & (1 << 26)) != 0)
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mips_bus_feq = (175*1000*1000);
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else
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mips_bus_feq = 233333333;
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} else {
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mips_cpu_feq = (500*1000*1000);
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if ((reg & (1 << 26)) != 0)
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mips_bus_feq = (125*1000*1000);
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else
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mips_bus_feq = 166666667;
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}
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}
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#elif defined(RT6352_ASIC_BOARD)
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/* FIXME */
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mips_cpu_feq = (600*1000*1000);
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mips_bus_feq = (133*1000*1000);
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#elif defined(RT71100_ASIC_BOARD)
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/* FIXME */
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mips_cpu_feq = (800*1000*1000);
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mips_bus_feq = (133*1000*1000);
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#elif defined (RT3883_ASIC_BOARD)
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clk_sel = (reg>>8) & 0x03;
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switch(clk_sel) {
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case 0:
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mips_cpu_feq = (250*1000*1000);
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break;
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case 1:
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mips_cpu_feq = (384*1000*1000);
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break;
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case 2:
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mips_cpu_feq = (480*1000*1000);
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break;
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case 3:
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mips_cpu_feq = (500*1000*1000);
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break;
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}
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#if defined (CFG_ENV_IS_IN_SPI)
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if ((reg>>17) & 0x1) { //DDR2
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switch(clk_sel) {
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case 0:
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mips_bus_feq = (125*1000*1000);
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break;
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case 1:
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mips_bus_feq = (128*1000*1000);
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break;
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case 2:
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mips_bus_feq = (160*1000*1000);
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break;
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case 3:
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mips_bus_feq = (166*1000*1000);
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break;
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}
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}
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else {
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switch(clk_sel) {
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case 0:
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mips_bus_feq = (83*1000*1000);
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break;
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case 1:
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mips_bus_feq = (96*1000*1000);
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break;
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case 2:
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mips_bus_feq = (120*1000*1000);
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break;
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case 3:
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mips_bus_feq = (125*1000*1000);
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break;
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}
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}
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#elif defined ON_BOARD_SDR
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switch(clk_sel) {
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case 0:
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mips_bus_feq = (83*1000*1000);
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break;
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case 1:
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mips_bus_feq = (96*1000*1000);
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break;
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case 2:
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mips_bus_feq = (120*1000*1000);
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break;
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case 3:
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mips_bus_feq = (125*1000*1000);
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break;
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}
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#elif defined ON_BOARD_DDR2
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switch(clk_sel) {
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case 0:
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mips_bus_feq = (125*1000*1000);
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break;
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case 1:
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mips_bus_feq = (128*1000*1000);
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break;
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case 2:
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mips_bus_feq = (160*1000*1000);
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break;
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case 3:
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mips_bus_feq = (166*1000*1000);
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break;
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}
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#else
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#error undef SDR or DDR
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#endif
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#else /* RT2880 ASIC version */
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clk_sel = (reg>>20) & 0x03;
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switch(clk_sel) {
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#ifdef RT2880_MP
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case 0:
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mips_cpu_feq = (250*1000*1000);
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break;
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case 1:
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mips_cpu_feq = (266*1000*1000);
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break;
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case 2:
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mips_cpu_feq = (280*1000*1000);
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break;
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case 3:
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mips_cpu_feq = (300*1000*1000);
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break;
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#else
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case 0:
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mips_cpu_feq = (233*1000*1000);
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break;
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case 1:
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mips_cpu_feq = (250*1000*1000);
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break;
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case 2:
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mips_cpu_feq = (266*1000*1000);
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break;
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case 3:
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mips_cpu_feq = (280*1000*1000);
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break;
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#endif
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}
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mips_bus_feq = mips_cpu_feq/2;
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#endif
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//RALINK_REG(RT2880_SYSCFG_REG) = reg;
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/* in general, the spec define 8192 refresh cycles/64ms
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* 64ms/8192 = 7.8us
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* 7.8us * 106.7Mhz(SDRAM clock) = 832
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* the value of refresh cycle shall smaller than 832.
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* so we config it at 0x300 (suggested by ASIC)
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*/
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#if defined(ON_BOARD_SDR) && defined(ON_BOARD_256M_DRAM_COMPONENT)
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{
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u32 tREF;
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tREF = RALINK_REG(SDRAM_CFG1_REG);
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tREF &= 0xffff0000;
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#if defined(ASIC_BOARD)
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tREF |= 0x00000300;
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#elif defined(FPGA_BOARD)
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tREF |= 0x000004B;
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#else
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#error "not exist"
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#endif
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RALINK_REG(SDRAM_CFG1_REG) = tREF;
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}
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#endif
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printf("CPU frequency: %lu\n", mips_cpu_feq);
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}
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