130 lines
3.2 KiB
C
130 lines
3.2 KiB
C
#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/scc.h>
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void SoC_Check_Device(void)
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{
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// This should run on a M829xx SoC, let's check it
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u32 devicetype = *(volatile u32*)(0x1008002C);
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if(devicetype != 0x140)
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{
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//error wrong device
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// TODO: what should we do?
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}
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}
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void SoC_PLL_init(void)
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{
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//sys_write_control(CR_M | CR_V | CR_ASYNC);
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u32 i = 0;//CR_M | CR_V | CR_ASYNC;
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/* turn off I/D-cache */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (CR_ASYNC);
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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HAL_set_amba_clk(133000000);
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HAL_set_arm_clk(450000000);
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}
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//void SoC_mem_init(int controller, int base, int length)
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void SoC_mem_init(void)
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{
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#if 0
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//*(volatile u32*)(0x10080010) = 0xD2db;
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//*(volatile u32*)(0x1008001c) = 0x42;
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//*(volatile u32*)(0x10080014) = 0xEA;
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*(volatile u32*)(0x10080010) = 0xD4E3;
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// Configure SDRAM CFG2
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*(volatile u32*)(0x10080014) = 0x00EA;
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//Configure SDRAM REFRESH
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*(volatile u32*)(0x10080018) = 0x0820;
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//Configure SDRAM PWRON
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*(volatile u32*)(0x1008001C) = 0x682B;
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*(volatile u32*)(0x10060000) = 0xF;
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*(volatile u32*)(0x1006000C) = 5;
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#else
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if (1)//controller == 0)
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{
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//matisse only have one SDRAM controller so the first param is useless
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// The following settings is based on a SDRAM with clock rate 133 MHz and speed grade -7
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// Configure SDRAM CFG1
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*(volatile u32*)(0x10080010) = 0xD4E3;
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// Configure SDRAM CFG2
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*(volatile u32*)(0x10080014) = 0x00EA;
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//Configure SDRAM REFRESH
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*(volatile u32*)(0x10080018) = 0x0820;
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//Configure SDRAM PWRON
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*(volatile u32*)(0x1008001C) = 0x682B;
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#if 0
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// The following settings is based on a DDR-SDRAM with clock rate 133 MHz and speed grade -75z
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// Configure SDRAM CFG1
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*(volatile u32*)(0x10080010) = 0xD6DA;
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// Configure SDRAM CFG2
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*(volatile u32*)(0x10080014) = 0x03EA;
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//Configure SDRAM REFRESH
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*(volatile u32*)(0x10080018) = 0x0820;
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//Configure SDRAM PWRON
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*(volatile u32*)(0x1008001C) = 0x682B;
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#endif
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if (PHYS_SDRAM > (128*0x100000)) { // high memory
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*(volatile u32*)(0x10060000) = (PHYS_SDRAM >>20)<<4;
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*(volatile u32*)(0x10060010) = (PHYS_SDRAM >>27);
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}
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else {
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*(volatile u32*)(0x10060000) = (PHYS_SDRAM >>16)<<4;
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}
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switch (/*length*/PHYS_SDRAM_SIZE/0x100000)
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{
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case 8:
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*(volatile u32*)(0x10060000) |= 0xB;
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break;
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case 16:
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*(volatile u32*)(0x10060000) |= 0xC;
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break;
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case 32:
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*(volatile u32*)(0x10060000) |= 0xD;
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break;
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case 64:
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*(volatile u32*)(0x10060000) |= 0xE;
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break;
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case 128:
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*(volatile u32*)(0x10060000) |= 0xF;
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break;
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}
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// Enable Chip select 0
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//*(volatile u32*)(0x1006000C) |= 0x1;
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//*(volatile u32*)(0x1006000C) = 0xC;
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if (PHYS_SDRAM > (128*0x100000)) // high memory : do ARAM remap to have memory @0x00000000
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*(volatile u32*)(0x1006000C) = 0x115;
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else
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*(volatile u32*)(0x1006000C) = 0x05;
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}
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#endif
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}
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void SoC_flash_init(void)
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{
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// Configure SDRAM CFG1
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*(volatile u32*)(0x10060004) = 0x0010000b;
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//*(volatile u32*)(0x10060014) = 0x10;
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*(volatile u32*)(0x10060014) = 0;
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*(volatile u32*)(0x10080004) = 0x0D92;
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*(volatile u32*)(0x1006000C) |= 2;
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}
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void SoC_nand_init(void)
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{
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*(volatile u32*)(0x1008000C) = 0x0492;
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*(volatile u32*)(0x1006000C) |= 8;
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}
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