99 lines
1.6 KiB
C
99 lines
1.6 KiB
C
/*
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* Copyright Codito Technologies (www.codito.com)
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*
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* cpu/arc/cpu.c
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*
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* Copyright (C)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Authors :Sandeep Patil (sandeep.patil@codito.com)
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* Pradeep Sawlani (pradeep.sawlani@codito.com)
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*/
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#include <command.h>
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#include <common.h>
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#include <asm/arcregs.h>
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#if CFG_UBOOT_ON_FLASH
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/* if uboot is on flash then boot agian from flash */
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void (*reset)();
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reset = (void (*)())0x0;
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(*reset)();
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#endif
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}
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void disable_icache(void)
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{
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__asm__ __volatile ( "lr r0,[0x11] \n\t"
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"or r0,r0,1 \n\t"
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"sr r0,[0x11] \n\t"
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::
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:"r0");
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}
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void dcache_disable(void)
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{
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/* Flush D cache */
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__asm__ __volatile (
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"sr 1, [0x47] \n\t"
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::
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);
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/* Disable D cache */
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__asm__ __volatile (
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"lr r0,[0x48] \n\t"
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"or r0,r0,1 \n\t"
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"sr r0,[0x48] \n\t"
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::
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:"r0");
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}
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dcache_enable()
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{
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}
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dcache_status()
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{
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}
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void flush_cache (unsigned long dummy1, unsigned long dummy2)
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{
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/* flushing data cache */
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write_new_aux_reg(ARC_REG_DC_FLSH, 1);
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/* poll for completion */
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while (read_new_aux_reg(ARC_REG_DC_CTRL) & (1<<8));
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/* Invalidate instruction cache */
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write_new_aux_reg(ARC_REG_IC_IVIC, 1);
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/* read will only comple when invalidation complete */
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read_new_aux_reg(ARC_REG_IC_CTRL);
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}
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/*
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* disable dcache and icahce
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*/
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int cpu_init(void)
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{
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disable_interrupts();
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return 0;
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}
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